JPS5893349A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an uneven pattern in uniform depth, and to obtain multilayer wiring structure having high density by etching one of laminated insulating films. CONSTITUTION:The SiO2 film 321 and the polyimide resin film 322 are shaped onto an Si substrate 31. The film 322 is selectively etched, and a concave section is formed. Difference at a stage of the concave section can be made constant because the speed of etching of the film 322 is larger than that of the film 321 at that time. An Al-Si film is coated through a sputtering method, and stage breaking is generated, thus forming wiring layers 331-332. A resist pattern 34 is shaped, and the unnecessary sections of the wiring layers 331-332 are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of forming a wiring structure of a semiconductor device which is becoming increasingly finer.

[Technical background and problems of the invention]

BACKGROUND ART Recently, lithographing technology, etching technology, etc. in semiconductor device manufacturing have progressed, and semiconductor devices are becoming more highly integrated and miniaturized. As semiconductor devices become increasingly finer, wiring patterns also become finer, and the spacing between adjacent wires also becomes finer.

As a result, a problem arises in that stray capacitance between adjacent wirings increases, which increases signal propagation delay.

FIG. 1 shows an example in which three parallel wiring layers 11 to 1m are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. now,
Assume that the width W and the interval days of wiring layers j1 to J are equal, and the middle O
When the wiring layer j is injected, the unit length sw associated with the bend is
The bo capacitance C is expressed as CxC + 20m where CI is the capacitance of the insulating film 2 and CI is the capacitance due to the gap between wiring layers. The change in capacitance C when the value of w-1it is varied is shown by the solid line O in FIG. 2. The one-dot chain line indicates the case where the capacitance due to the insulating film 2 is zero.
ax and 11 #1! ′ shows the minimum value at equal points,
This increases as the dimensions become even more subtle. This is the capacity C
This is because the rate of increase in the capacitance C8 is greater than the rate of decrease in I.

As described above, as wiring becomes finer, delays in signal propagation due to increased capacitance become a serious problem. Further, miniaturization of wiring by the conventional method brings about a decrease in current capacity, an increase in wiring resistance, and disconnection due to electro-irrasis, leading to a decrease in the reliability of semiconductor devices.

[Purpose of the invention]

The present invention significantly reduces the capacitance associated with wiring layers, thereby suppressing delay in signal propagation due to miniaturization of interconnections, and further miniaturization of interconnections using conventional phosphorography technology. The present invention provides a method for manufacturing a semiconductor device that can easily achieve high integration without any additional steps and can significantly improve reliability.

[Summary of the Invention] The present invention is a method of disposing a wiring layer having parallel adjacent portions formed in the same conductive film forming process with an insulating film interposed therebetween on a semiconductor substrate on which an element region is formed. hand,
First, a first film made of different materials is placed on a semiconductor substrate. A second insulating film is sequentially deposited and selectively etched to form irregularities corresponding to the wiring pattern.

At this time, by using an etching method in which the etching rate for the second insulating film is sufficiently higher than that for the first insulating film, the first insulating film is reliably kept constant as the etching stop Δ*-a; form a recess. Thereafter, a conductor film is applied over the entire surface to form parallel adjacent wiring layers separated by the uneven step portions.

〔Effect of the invention〕

l・.

According to the present invention, it is possible to form an uneven Δ turn with a uniform depth and good reproducibility using a laminated insulating film, and the uneven I
One of the four parallel and adjacent portions of the wiring layer made of the same conductive film that is self-aligned to the pattern and in good condition is disposed in the concave portion and the other in the convex portion. Therefore, adjacent wiring layers do not directly oppose each other, or even if they do, the opposing area can be made extremely small, so the capacitance between wirings is small, and signal propagation in wiring is delay becomes smaller.

Moreover, since the depth of the unevenness is uniform, there is no variation in capacitance 4 associated with the wiring layer, and the capacitance 4 is uniform.

In addition, the separation distance in the horizontal direction between adjacent wiring layers (O) is almost zero (To), so that even if the wiring width is not made very fine, the wiring density can be increased to achieve even higher integration of the device. t
Since the wiring width does not have to be made so small, high integration of semiconductor devices can be easily achieved using conventional lithography technology. For the same reason, it is possible to prevent reduction in the current capacity of the wiring O, disconnection due to electromider radiation, and increase in resistance, thereby improving the reliability of the semiconductor device.

[Embodiments of the invention]

FIG. 3 shows a cross section of a main part according to an embodiment of the present invention. Reference numeral 11 denotes a substrate 81 on which an element region is formed, and a first and second insulating film 121.1 made of different materials is formed on this substrate.
Three wiring layers 131 adjacent to each other in parallel with each other via 21
~13s was formed. The first insulating film 121 is, for example, 0.5 μm thick, and the second insulating film 123 is, for example, 1 μm thick.
By selectively etching the second insulating film 123, a concavo-convex pattern with steep steps of about 1 μm is formed corresponding to the interconnection grooves.
~J'Js is made of the same conductive film that is thinner than the uneven steps.
The wiring layer 1B in the middle is in the recess, and the wiring layer on both sides is 1 m 13
B is arranged on the convex portion. The horizontal distance between wiring layers 13□ to 13° is almost zero. With such a wiring structure, as is clear from the comparison with Figure 1, the capacitance associated with the wiring layer is extremely small. small,
Furthermore, it can be seen that since the separation distance is almost zero, it is possible to improve the wiring density and achieve a significantly higher degree of integration.

FIG. 4 shows an example in which similar wiring structures are stacked in multiple layers. That is, a laminated insulating film 221 is formed on the 81 substrate 21.

22. The first of three is separated by the unevenness of its surface through the
Layer wiring layers 231 to 23 are formed, and a laminated insulating film 24 is similarly formed thereon. ．． 24. Three second-layer wiring layers 251y:1M are formed on the surface of the wiring layer 251y separated by unevenness. This makes it possible to realize a high-density multilayer wiring structure.

FIGS. 5(a) to 5() are diagrams for explaining the manufacturing process of an embodiment of the present invention. First, a first insulating film is formed on a substrate 31 having an element region formed thereon. A 32mm thick 8102 film was formed by CVD to a thickness of 174mm, and a second insulating film was coated on top of this using a spin code.
1μm polyimide resin film 12 baked at 00℃
Form 3 (Xun.

Next, the -limide resin film 32 is selectively etched using a photoetching method to form a recess (b). At this time, keratin dry etching is performed using a mixed gas of CF4 and 02. When using the 5102 film 321, the etching speed of the polyimide resin film 32 layer is sufficiently higher than that of the 5to2 film 32@, so even if over-etching is performed, the 5102 film 321 is hardly etched, and the 5102 film J is reliably etched on the bottom surface of the recess.
2M can be exposed. That is, it is possible to obtain a state in which the level difference in the recess is constant with good controllability and reproducibility. In this case, the concave portion corresponds to the middle wiring Ils/4 turn of the three parallel wiring layers formed thereon. Thereafter, a μ-81 film as thin as 1/2 of the step of the concave portion is deposited on the entire surface by sputtering, and the 9 μm 81 wiring layers 331 to 331 to Jj are separated from each other by creating a cut at the step.
.

(C)0 Next, form a resist i4 turn J4 by a normal PEP process (this resist) /
U-81 wiring 411°4J using 4 turns 34 as a mask
Unnecessary portions of a are removed by etching to obtain a predetermined wiring width (.).

According to this embodiment, the conventional lithography technique is
1, and by actively utilizing step breaks, it is possible to reduce the interlayer capacitance and realize high 11[wirings] without any difficult microfabrication. ,6. Particularly when applied to a large-scale integrated circuit with a large wiring area such as a CPU, effects such as reduction in chip/area, higher integration, and higher reliability can be obtained. Furthermore, by using laminated insulating films with different etching resistance in this embodiment, unevenness of uniform depth can be obtained without unevenness due to over-etching, thereby increasing the capacitance between wiring layers. By making it uniform and small, it is possible to further improve the performance of the semiconductor device. Furthermore, since the specific fermentation rate of the resin membrane is about 3.0, it is preferable in terms of reducing the capacitance associated with the wiring layer compared to the case of using only the 8-02 membrane.

FIG. 6 shows a wiring structure obtained by modifying the above embodiment. That is, a 5102 film 421 and a polyimide resin film 42 are laminated on the Sl substrate 4J, and a predetermined uneven pattern is formed by selectively etching the polyimide resin film 428. Then, as in the above embodiment, by depositing an AA-81 film thinner than 1/2 of the level difference between the convexes and convexities,
Adjacent to each other in parallel, separated by uneven steps. u
-Si wiring layers 43t to 4M are formed.

In this case, in the process of etching away unnecessary portions of the wiring layer 431e43m in the flat portion, a wire 436 is formed at the same time when a large wiring such as a power supply line is required.

Thus, according to this embodiment, the signal wiring portions that are closely adjacent to each other in parallel to each other and the power wiring portions that require a large current capacity can be skillfully made to coexist while satisfying their respective required performances.

In each of the above examples, polyimide/8102 was used as the insulating film combination, but 81sN4/S102-
? Other combinations can also be used, such as ht2oA/s to2. In addition, as a method for separating wiring layers at step portions, instead of using a step cut, a conductive film is deposited on the entire surface and then a mask material is used as a mask material that increases the etching rate at the step portions, such as 5to2 by glazma CVD.
A method may also be used in which a film is formed, the entire surface is etched, only the stepped portion of the 7S102 film is removed, and the conductor film is selectively etched using the remaining 5102 film as a mask. Further, in the embodiment, an Aj-81 film was used as the conductor film, but metals such as hLpW, various silicides, polycrystalline silicon, etc. may also be used.

In each of the above embodiments, the case where three parallel wiring layers are mainly formed has been explained.

Therefore, after separating the wiring layers at the uneven step portions, the wiring layers at the flat portions are Δ turned by a normal PEP process. However, for example, when a large number of wiring arm turns are arranged parallel to each other over the entire surface of the substrate, adjacent wiring layers can only be separated by a concavo-convex pattern on the surface of the insulating film corresponding to the wiring/f-turn. , the subsequent normal PEP process is not necessary. Even in the case where the conductor film remaining on the flat part is left as is, for example, in a shield-1 manner, after separating a multi-layered wiring pattern at an uneven step part, the subsequent PAP process can be similarly omitted. Furthermore, in each of the above embodiments, the middle one of the three parallel adjacent wiring layers is placed in the recessed part to separate the wiring on both sides. Of course, it may be formed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the wiring structure of a conventional semiconductor device, and FIG. 2 is a diagram showing the relationship between the wiring width and the stray capacitance of the wiring.
FIG. 3 is a diagram showing an example of the wiring structure according to the present invention, FIG. 4 is a diagram showing an example in which two layers of the same wiring structure are laminated, and FIG.
1) to (・) are diagrams showing the manufacturing process of one embodiment of the present invention,
FIG. 6 is a diagram showing the wiring structure of a modified embodiment. 11, :11,31,41...S1 substrate, 12I. 22 凰 al14@ 131@ , 421...first insulating film, 12 proverbs # 2 J @ @ j 4
@ e J j Tomi, 42 fable...Second insulating film, 1
31~JJap2Jbreath~zs,,z5~ztiaess
*〜jJa. 431-43s...Wiring layer applicant's agent Patent attorney Takehiko Suzue No. 1II *2 Figure 3 Figure 4 Figure 5 Figure 5

Claims (1)

[Claims] The step of forming a first insulating film on a semiconductor substrate and then forming a second insulating film made of a material different from the ml insulating film, and the etching rate of the second insulating film compared to that of the first insulating film, are performed. A step of selectively etching the second insulating film using a sufficiently large etching method to form unevenness corresponding to the wiring pattern, and a step of depositing a conductive film on the entire surface and forming IiI in parallel to each other separated by the stepped portions of the unevenness. 1. A method of manufacturing a semiconductor device, comprising the step of forming a contacting wiring layer.