JPS61121347A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield and reliability and the like of a semiconductor device, and to increase density by forming a conductive material layer on a substrate, shaping an inter-layer connecting section, which is left as it has the thickness of the conductive material layer, and a first layer wiring having the intermediate thickness of the conductive material layer and forming a second layer wiring on an insulating layer as an inter-layer insulating film and the inter-layer connecting section. CONSTITUTION:A novel resist 14 is used, and an aluminum layer 12 is patterned, thus shaping a first layer wiring. A PSG layer 15 is deposited through CVD, and an application type insulating film constituting of PLOS (Poly Ladder Organ Silicate), etc. is applied onto the layer 15, and baked. An SiO2 film 16 and the PSG film 15 are etched is succession from a top surface through reactive ion etching employing a Freon group gas, and etching is stopped when the top surface of an inter-layer connecting section in the aluminum layer 12 is exposed completely. A second aluminum layer is deposited on the top surface of the inter-layer connecting section, and a second layer wiring 17 is obtained through patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of industrial application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for creating highly reliable and highly charged multilayer wiring.

[Conventional technology]

A typical conventional multilayer wiring method will be explained with reference to FIG. For example, an aluminum layer 2 with a thickness of about 1 μm is deposited on the substrate 1 and patterned using a resist 3 to obtain a first layer aluminum wiring 2 (FIG. 3A). Next, for example, a PSG layer 4 with a thickness of 1 μm is deposited as an interlayer #l film, and a through hole (also referred to as a pier hole) 6 is opened using a resist 5 (FIG. 3B). Then, P.S.G.
A second aluminum layer 7 is deposited to a thickness of about 1 μm on layer 4 and in through hole 6, and patterned using a resist (not shown) to obtain second layer aluminum wiring 7. This second layer aluminum wiring 7 is connected to the first layer aluminum wiring 2 via a through hole 6.

[Problem that the invention seeks to solve]

In the multilayer wiring method using through holes as described above,
Since there is a step in the through-hole portion when depositing the second layer wiring, there is a drawback that the second RF4 wiring is likely to be disconnected at the portion where the step is filled.

In addition, since there are two alignment steps, one between the first layer wiring 2 and the through hole 6, and the other between the through hole 6 and the second layer wiring ls7, the first layer wiring 2 and the second layer wiring are It is necessary to make the dimension of the through-hole forming area of the wiring ls7 larger than a specific value. Referring to FIG. 4, the width of each wire 2°7 is not critical, but is, for example, 3 μm.
Then, the through hole 6 is about 2 μm x 2 μm wide, and the 6-way 1 FIJ2.7 pattern placed at the through hole 6 position has a different dimension of about 6 μm x 6 μm (this widened part is commonly called the "pier pad"). ).

However, the via pads in the second layer are not only used to provide alignment margins, but depending on the method of depositing the second layer wiring, the height difference in the through holes may cause
Sometimes you cannot expect a reliable connection (i.e., some of the four sides of the through hole may not be connected between layers 1 and 2), so
A certain amount of size is required in order to ensure that the first and second layer wirings are connected at the sides and connected through the periphery of the through hole. These via pads become a factor that restricts changes in wiring density when semiconductor devices change in density.

[Structure of the invention]

In order to solve the problems of the prior art as described above, the present invention provides (1) a conductive material layer with a total thickness of the first layer wiring to be formed and the glabella insulating film on the substrate; and (
2) Selectively etching the conductive material layer with respect to both its planar shape and thickness to increase the thickness of the conductive material layer for electrically connecting the first layer wiring and the second layer wiring. With the remaining interlayer connections.

A first layer wiring having a thickness intermediate to that of the conductive material layer is formed, and (
3) After depositing an insulating layer on the first layer wiring, the interlayer connection, and the substrate, etching the insulating layer halfway to planarize the surfaces of the insulating layer and the interlayer connection, and Provided is a method for manufacturing a semiconductor device, comprising the steps of: exposing the top of the interlayer connection; and (4) forming a second layer wiring on the insulating layer forming an interlayer insulating film and the interlayer connection. do.

[For production]

According to the method of the present invention, when depositing the second layer wiring, there is no risk of disconnection of the second layer wiring due to a step difference since the surface of the underlying glabella insulating film and the interlayer connection portion are flat. As a result, the mutual alignment margin in turning of the first layer wiring, the interlayer connection portion, and the second layer wiring is kept to a minimum, which contributes to high density changes in semiconductor devices.

〔Example〕

The present invention will be described in detail with reference to FIG.

In the present invention, first, for example, aluminum 1i912 is deposited on the base 8211 to a thickness of, for example, 2 μm. Then, a resist 15 is placed on this thick aluminum layer 12.
, leave the resist 13 only at the interlayer connection part (corresponding to the conventional pier hole part), and use the resist pattern 13 as a mask to cover the aluminum layer 12 halfway, leaving an aluminum layer with a thickness of, for example, 1 μm. Selective etching is preferably performed using an anisotropic etching method (FIG. 1A).

Next, the resist 13 may be removed or removed, but
Using a reliable resist 14, the aluminum layer 12, which has a thickness of 1 μm and is to be fabricated, is patterned to form an NX1 layer wiring. At this time, rf! 1 connection indirect thickness part 2μm remains (Fig. 1B) 4th order 2, 91J, t, CV
DfPSG! After depositing 15 layers with a thickness of 1.5 μm (
Figure 1 C), and roughly on top of it, for example, P L O8 (Po
1y 'Ladder OrganSillcate
) is coated with a coating type insulating film of about 2 μm in thickness and fired. When fired, the aPLO 8 becomes an 8102 film 16, but its surface is flat due to the coating type (FIG. 1D).

Then, anisotropic etching is performed in which the etching speed of the 5in2 film 16 and the PSG film 1 film 5 or the aluminum re 12 is controlled to be equal, for example, hexagonal reactive ion etching using Freon gas (CF4+04F8). , 5202 film 16, and then the top five surfaces of PSG film 1. Etching is then stopped when the top surface of the interlayer connection portion (2 μm thick portion) of aluminum #12 is completely exposed. Then, the first
As seen in Figure E, the aluminum layer 12 is covered with an interlayer insulating film 15.16, and only the aluminum layer 15 and
A force S produced by eJz force Zg and a flat top surface can be obtained.

If a second aluminum layer is deposited on this layer with a thickness of about 1 μm and patterned, a second layer wiring 17 can be obtained.
Since the two-layer wiring 17 with group 1 (FIG. 1F) a is deposited on a flat base, no step is formed and there is no fear of disconnection.

As a result, the alignment margin for patterning the first aluminum layer 12 and the second aluminum layer 17 can be significantly smaller than in the conventional method. For example, as shown in Fig. 2, the second layer wiring 17 and the second layer wiring 17 may have the same width, for example, 3 μm. Chopsticks 1st layer wiring; s12 and 2nd layer wiring 17
For example, even if there is a misalignment, as long as they are in contact with each other at some point, the mutual contact points are flat and are sufficient for electrical contact.

Although the present invention f has been described above with reference to one embodiment, the present invention is not limited to the specific matters of this embodiment. For example, when patterning the first aluminum layer, a wiring pattern including interlayer connections may be created first, and then only the wiring portion excluding the interlayer connections may be etched to an intermediate height. The method is not limited to the above, and the material of the distribution layer and the insulating layer,
The shape, dimensions, processing method, etc. are not limited to those described above.

〔Effect of the invention〕

According to the present invention, in a multilayer wiring, the upper layer wiring is deposited on a flat base. Therefore, there is no risk of wire breakage. Therefore, the quality and reliability of the semiconductor device are improved. Since there is no fear of disconnection (steps), the alignment margin between each wiring layer and the interlayer connection portion (corresponding to a conventional through hole) can be significantly reduced, which contributes to higher density opening of semiconductor devices.

[Brief explanation of drawings]

1 & -F are cross-sectional views of main parts of a semiconductor device in the order of steps in the implementation row of the present invention, FIG. Semiconductor device process order! FIG. 4 shows a plan view of a through-hole portion of a conventional multilayer wiring. 1... Substrate 2... First layer wiring 4... Interlayer insulating film 6... Through hole... 1π2 layer wiring 11... Substrate 12... First layer wiring and interlayer connection part 15.16...
・I-layer 17... Margin below 2nd layer wiring Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. (1) Form a conductive material layer on the substrate to a total thickness of the first layer wiring and the interlayer insulating film to be formed, and (
2) Selectively etching the conductive material layer with respect to both its planar shape and thickness to increase the thickness of the conductive material layer for electrically connecting the first layer wiring and the second layer wiring. forming a first layer wiring having a thickness intermediate between the remaining interlayer connections and the conductive material layer, and (3) depositing an insulating layer on the first layer wiring, the interlayer connections, and the substrate; , etching the insulating layer halfway to planarize the surfaces of the insulating layer and the interlayer connection part and exposing the tops of the interlayer connection part, and (4) etching the insulating layer and the interlayer connection part forming an interlayer insulating film. A method for manufacturing a semiconductor device, comprising the step of forming a second layer wiring on a connection portion.