JPS6020523A - Electronic device - Google Patents

Abstract

PURPOSE:To make the thickness of an inter-layer insulating film formed on an extended wire the same as that of a wiring section, and to enable flat element structure, etc. by forming the comparatively narrow extended wire outside a bonding pad and bringing each conductive layer constituting the pad into contact in the extended wire section. CONSTITUTION:Aluminum is evaporated on the surface of a semiconductor substrate 1, and the surface is coated with a mask, to which a first layer wiring pattern in an internal circuit is formed, and etched, thus simultaneously forming a first layer wiring and a first layer conductive layer 3a. A first inter-layer insulating film 2a is shaped on the wiring and conductive layer through deposition technique for SiO2 by sputtering. Consequently, an SiO2 film is formed thinly on a narrow aluminum wiring, and the SiO2 film is formed on other sections comparatively thickly, thus shaping the surface of the first inter-layer insulating film 2a approximately smoothly as a whole. Accordingly, the width of a second layer aluminum wiring formed through masking and etching after a contact hole is formed to the first inter-layer insulating film 2a and aluminum is evaporated on the contact hole can be made thinner than the case there is irregular sections.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to electrode technology and a multilayer wiring structure, for example, to a technique that is effective when applied to the formation of a t-pole in a semiconductor device. be.

[Background technology]

The present inventor has developed the following technology regarding 1tfii technology, particularly multilayer wiring technology for semiconductor devices.

That is, semiconductor integrated circuit (hereinafter referred to as LSI)
As the degree of integration increases, wiring for connecting elements becomes more complex, so two or three layers of wiring are formed on the surface of the semiconductor chip with an insulating film interposed therebetween. In this case, each distribution /f? An interlayer insulating film such as silicon oxide (S + 02), which is formed for insulation between y-layers, is formed using, for example, the CVD method (
When formed by chemical vapor deposition method), the glabellar insulating film is formed to have a substantially uniform thickness over the entire chip. Therefore, depending on the unevenness of the first layer wiring β1+#2+... formed on the surface of the semiconductor chip 10, the surface of the interlayer insulating film 2 becomes smooth as shown in FIG. This will result in unevenness. As a result, the second
The wiring formation and connection after the 5th layer are no longer required. Therefore, an attempt is made to smooth the surface of the interlayer insulating film 20 as shown in FIG. 1(2) by forming an insulating film between the eyebrows using a Si02 film deposition technique using bias sputtering.

However, in such a technique, in a relatively narrow wiring portion, the surface of the first interlayer insulating film is smoothed by forming the interlayer insulating film 2 to be thinner than the pond portion, but the bonding pad Regarding the electrode part with a relatively large area like 3.

The center portion becomes equal to the surface of the semiconductor chip 10, and the interlayer insulating film 2 is formed thicker than the wiring portion, as shown in FIG.

However, when LSIs are connected by three-layer wiring made of aluminum or the like, it is not specified which layer of wiring is connected to the bonding pad.

The bonding pad part is also made of aluminum as shown in Figure 3.
It is often necessary to have a layered structure.

Seven Danu, when the interlayer insulating film is formed by the sputter SiO method as described above, through holes are formed in one interlayer insulating film to make contact between wirings and contact between each layer of the above-mentioned bonding pad. .

If the interlayer insulating film is etched in accordance with the wiring portion, the insulating film will not be completely removed at the bonding pad portion and will remain, making it impossible to make contact between the conductive layers constituting the electrodes. It has been found that if the interlayer insulating film is etched in accordance with the bonding pad portion, the problem arises in that even the aluminum wiring is etched away in the wiring portion.

[Purpose of the invention]

One object of the present invention is to provide an electrode technique that exhibits significant effects.

Another object of the present invention is to provide a process technology suitable for multilayer wiring structures.

Another object of the present invention is to provide an electrode technology that enables a flat device structure.

Another object of the present invention is to provide an electronic device that allows easy electrical measurements during one manufacturing process.

The main feature of this invention is 1. For example, when applied to MSs such as bonding pads in semiconductor devices, it is possible to form multilayer electrodes without adversely affecting wiring parts, regardless of the method of forming a single interlayer insulating film. The object of the present invention is to provide an electrode technology that allows sufficient contact between conductive layers.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A summary of typical inventions disclosed in this application is as follows if mJ is simply 1 Haramachi.

That is, the present invention provides, for example, a relatively It'! It forms a narrow study area.

By making contact between the conductive layers constituting the band at this extended line portion, the interlayer insulating film formed on the extended line can be made to have the same thickness as the wiring portion.

This aims to achieve the above objectives.

This invention will be concretely explained below using the drawings.

〔Example〕

No. 41 ¥1 is an example of the semiconductor device 14 of the present invention in which only one bonding pad VC is used.

In this embodiment, in correspondence with the three-layer aluminum wiring technology used for connection of internal circuits, three conductive M3'' r3 layers made of aluminum evaporated layers, etc., similar to the one in Fig. 3 are used.
By polymerizing b and 3c, 41・v
has been completed. That is, aluminum is vapor-deposited on the surface of the semiconductor board, and then etching is performed while covering with a mask on which the first-layer wiring pattern of the internal circuit is formed. The second conductive layer 3a is formed at the same time, and then sputtered SiO
By sputtering called method. The first interlayer insulating film 2a (see Fig. 3) is formed by SiO deposition technology.
be formed. Therefore.

A thin film of Sin is formed on the narrow aluminum wiring,
In other parts, 5in2 films are formed relatively 19 times (19 times), as shown in Fig. 1 (2) or Fig.
The surface of the interlayer insulating film 2a is formed to be substantially smooth as a whole, so that the first JPIf14] insulating film 2a
By forming a contact hole on the contact hole, depositing aluminum on the contact hole, and then masking and etching it, the width of the second layer of aluminum wire RA can be made narrower than when the contact hole is uneven. , it becomes possible to form fine wiring. Simultaneously with the formation of the second layer of wiring, the second layer of conductive layer M3b of the pump throat 3 is formed.

Furthermore, in the case of three-layer aluminum interconnection, a second interlayer insulating film 2b is formed on the second layer of aluminum wiring, and a contact hole is formed in this, and then the aluminum The third layer of wiring and the third conductive layer 3C of the bonding pad are formed by vapor deposition, polishing, and etching with repeated turns.

Then, a final vacuum film 4 such as a p-3iO film is formed by plasma deposition on the third layer wiring, and the pumping area is etched. Pad opening 4
A is formed.

Note that - the deposition method of the second interlayer insulating film 2b does not have to be the sputtering SiO method described above.
OG (spin on glass) film and PSG (phosphorus) film
A three-layer structure of silicon, glass, etc. can also be used.

However, in this example, the above-mentioned pounding pad 3
Each conductive layer: 3a, 3b, 3c are all 2
44M. Ding, that is,
In each of the conductive layers 38 to 3C, 44 is the pad portion 31 which is the main electrode portion of Ichiman J Cedar, and this pad portion 3! It consists of 41 extending AIQs 32a to 32f formed so as to protrude in parallel from one side at an appropriate distance of 11η from each other. The pad portion 31 is formed to have the same size as a normal bonding pad, and the extension line portion 32 serves as a reinforcing portion to which the input/output signal line of the internal circuit or the wiring of the power supply line is connected. It is being done. This reinforcing portion is provided to prevent the connection between the pad and the wiring from being broken due to damage to the nearby wiring when the bonding wire is connected to the pad 31.

The extensions 1J32a to 32f are formed to have a width of, for example, 5 μm or less, which is necessary to realize the flat I'1 state of the interlayer insulating film formed by sputtering SiO method, and In order to increase the number of wires as much as possible, they are formed in parallel with an interval of, for example, 35 μm, which is the same as the minimum wiring interval in the internal circuit.

As a result, in the bonding pad of this embodiment, contact between the layers is made not at the pad portion 31 but at the extended line portion 32. In other words, as explained in the background art section, when an interlayer insulating film is formed by the sputter SiO method, a large area of the bonding pad is formed by the center part excluding the edge (approximately 5μff1ll area). Above, as shown in FIG.
1°1 more than 3! 3 The membrane 2 is formed,
Therefore, when the insulating film 2 is etched to form a contact hole along the 5 wiring portions, the insulating film at the center of the pad is not completely removed and remains. However, in this embodiment, a '4# with a width of 5 μm or less is placed outside the pad portion 31.
Since lines 32a to 32f have been destroyed, this extension line 3
On 2a to 32f, a relatively thin interlayer insulating film similar to that on the wiring is formed by sputtering. Otherwise, the insulating film on the extended line portion 32 can be completely removed by etching it in accordance with the wiring portion of the circuit. As a result, each of the conductive layers 3a to 3 of the bonding pad 3
C, as shown in FIG. 5, contact between the layers is made at the extended line portion 32.

Further, the wiring connection to the bonding pad 3, which has made interlayer contact with the extended wire portion 32 in this way, is made by connecting the wiring to the bonding pad 3, which has made interlayer contact in this way. 32a to 32f, a connecting portion L continuous with the wiring is provided so as to intersect with these as shown in Fig. 4.
This is done by forming a.

In the above embodiment, the extension line part 32 also serves as the throat reinforcement part, but the invention is not limited to this, and as shown in FIG. Contact between pad layers may be achieved by protruding extension lines 32a to 32C from each of the conductive layers 3a to 3C and connecting them 12!! When the line portion 32 and the reinforcing portion 33 are arranged in the same order, it is possible to ensure contact between the eyebrows without increasing the area occupied by the conventional pad.

It should be noted that, instead of forming the extended line portion 32 in the shape of a trap strip as in the above embodiment, it may be possible to form it in the form of a lattice of lines of 5 μm or less, or in the form of a mesh. In the example, the current deposition technology using sputter SiO method is used.

Although the width of the extended line was determined to be 5 μm or less, the width of the line is not limited to such a value, and of course can be arbitrarily determined in relation to the deposition technique.

〔effect〕

A relatively narrow extension line is formed on the outside of the pad section which is the main electrode section, protruding from the pad section by 1°, for each conductive layer. By doing so, there is no need for contact between each conductive layer in the pad area, so sputtered Si
Even if a smooth interlayer insulating film is formed by the O method, the conductive eyebrows of the pads can be brought into reliable contact without any adverse effects due to etching on the wiring portion.

In addition, by connecting the wiring of the internal circuit and the pad with an extension line protruding from the pad part, and bending the reinforcement part by 1j°C, the reinforcement part and the extension line can be connected separately to the pad part. This eliminates the need to protrude outward from the pad, which has the effect of allowing contact between conductive layers without increasing the area occupied by the pad.

Although the invention made by the present inventor has been specifically described above based on examples, it is to be noted that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without understanding the gist thereof. Not even.

For example, the present invention can be applied not only to a bonding pad having a three-layer structure, but also to a two-layer structure or a bonding pad having four or more layers. In addition, in the above explanation, the case where the first layer Ak pad is connected to the paper board is described, but it can naturally be applied to the case where the above A and 6 bands are on the first layer insulating film. [Field of Application] In the above explanation, the invention made by the present inventor was mainly explained in terms of the application field of semiconductor devices, which is the background of the invention, but it is not limited thereto. It can also be applied to electrode technology.

In other words, the present invention can be applied not only to p-type interlayer insulating film formation processes but also to devices that use a method with film forming characteristics such as the sputter SiO method. Needless to say, the present invention can also be applied to electronic devices and the like.

In the body I; Alt side view of the board, Figure 2 is a cross-sectional view showing the difference in interlayer insulation between the wiring part and pad part using the Subalter SiO method, and Figure 3 shows an example of forming a bonding pad. Surface diagram.

FIG. 4 is a cross-sectional view of a bonding band showing an embodiment of the present invention, and FIG. 5 is a sectional view taken along the line v--■ in FIG. 4.

FIG. 6 is a plane +': J, + showing another embodiment of the present invention.

Semiconductor substrate for 1, 2, 2a, 2b... residue IN+insulating film.

3... Electrode device (ponding pad), 33-3c
... conductor layer, 31 ... main tti part (pad part),
32a to 32f...GP line, 33...Reinforcement part.

Claims (1)

[Claims] 1. It has an electrode structure formed by two or more conductive layers, and a relatively narrow extension line protruding from the main electrode part is formed for each conductive layer on the outside of the main electrode part. An electronic device having an electrode structure in which each conductive layer is contacted at the part of the wiring. 2. Main 1 above! 2. The electronic device according to item 1, wherein the pole portion is a bonding pad formed on a semiconductor chip. 3. The electronic device according to claim 2, wherein the extending line is formed to also serve as a reinforcing portion for the bonding pad.