JPS58197844A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce electrostatic capacitance accompanied by a parallel wiring layer isolated by the stepped difference section of a rugged surface section largely, and to inhibit the delay of signal propagation due to the miniaturization of wiring by forming the rugged surface section of a predetermined pattern having steep stepped difference to the surface of an insulating film and forming the wiring layer. CONSTITUTION:A SiO2 film 32 is formed onto a Si substrate 31 to which an element region is formed, and a concave section of approximately 1mum stepped difference is formed to the surface of the SiO2 film 32 through reactive ion etching while using a photo-resist as a mask. A phosphorus doped polycrystalline silicon film 33 is deposited on the whole surface, and a SiO2 film 34 is deposited on the film 33 by approximately 1.0mum as a mask material. The whole surface is etched by using NH4F, and the stepped difference section of the SiO2 film 34 is removed selectively through etching. Only the polysilicon film 33 of the stepped difference section is changed into oxide films 35 by selectively oxidizing the polysilicon film 33 through a combustion oxidation method while using the residual SiO2 film 34 as a mask. The recessed sections are buried completely with the polysilicon film 33 and the thermal oxide films 35 of the SiO2 film 34 because the volume of the thermal oxide films 35 is increased up to approximately twice as large as the polysilicon film 33 at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a wiring structure and a method for forming the same in a semiconductor device that is highly integrated and miniaturized.

[Technical background of the invention and its problems] Recently, ring graphing technology, etching technology, etc. in semiconductor device manufacturing have progressed, and semiconductor devices are becoming more highly integrated and miniaturized. As semiconductor devices become increasingly finer, wiring patterns also become finer, and the spacing between adjacent wires also becomes finer. As a result, a problem arises in that stray capacitance between adjacent wirings increases, which increases signal propagation delay.

FIG. 1 shows an example in which three parallel wiring layers 31 to 33 are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. now,
Assuming that the width W and the spacing S of the wiring layers 31 to 3s are equal, and focusing on the middle wiring layer 33, the associated capacitance per unit length is 1ttca, the capacitance of the insulating film 2 is Cm, and the capacitance due to the gap between the wiring layers. f Cs is expressed as C=C1+20 snow. The experiment shown in FIG. 2 shows how the capacitance C changes when the value of w-8 is changed. The one-dot chain line represents the case where only the capacitance C due to the insulating film 2 is present. As is clear from the figure, the capacitance C is determined by the film thickness To of the insulating film 2 when W=8.
Point A, which is approximately equal to x, represents a minimum at, which increases as the dimensions become finer. This is because the rate of increase in the capacity t Cm is greater than the rate of decrease in the capacity c1.

As described above, as wiring becomes finer, delays in signal propagation due to increased capacitance become a serious problem.

Further, miniaturization of wiring by conventional methods results in a decrease in current capacity, an increase in wiring resistance, disconnection due to electromigration, etc., which leads to a decrease in the reliability of semiconductor devices.

[Purpose of the invention]

The present invention aims to significantly reduce the capacitance associated with wiring layers, thereby suppressing delay in signal propagation due to miniaturization of wiring,
Furthermore, the present invention provides a method for manufacturing a life-death conductor device that uses conventional phosphorography technology to easily achieve high integration without further miniaturization of wiring, and that improves reliability.

[Summary of the invention]

The present invention provides a semiconductor device comprising a wiring layer gold film formed on a semiconductor substrate in the same conductive film formation process via an insulating layer, and having central portions adjacent to each other in parallel. A suitable pattern of unevenness with steps is provided, and one of the parallel adjacent portions of the wiring layer has a concave portion, and the other portion has a horizontal separation distance of #’! ! It is characterized in that it is arranged so that ff is zero, in other words, it is characterized in that it has nine parallel wiring layers separated by uneven step portions.

In forming the wiring structure as described above, the present invention first forms irregularities corresponding to the wiring pattern on the surface of the insulating film on the semiconductor substrate on which the element area is formed, and then overlays the entire surface. A conductive film is deposited, and then a masking material with a high etching rate is deposited on the entire surface of the conductive film at the stepped portions, the entire surface is etched, and this masking material is selectively removed at the uneven steps, and the remaining masking material is removed. In step 4111, the conductor film is selectively made into an insulating film using the method to form nine wiring layers adjacent to each other in parallel and separated by uneven step portions.

〔Effect of the invention〕

According to the present invention, one of parallel and adjacent portions of wiring layers made of the same conductive film is disposed in the concave portion and the other portion is disposed in the convex portion in a self-aligned state with the concavo-convex pattern. Therefore, adjacent wiring layers do not directly oppose each other, or even if they do, the opposing area can be made extremely small, which reduces the capacitance between wirings and improves signal propagation in the wiring. delay becomes smaller. Furthermore, the distance between adjacent wiring layers in the horizontal direction is almost zero, so even if the wiring width is not made very fine, the wiring density can be increased to achieve even higher integration of the device. Further, since the wiring width does not have to be made so narrow, it is possible to easily achieve high integration of semiconductor devices using conventional phosphorography technology. For the same reason, the reliability of the semiconductor device can be improved by preventing reduction in the current capacity 1 of the wiring, disconnection due to electromigration, and increase in resistance.

In addition, by embedding the deteriorated insulating film into the stepped portion of the uneven portion formed on the insulating film according to the wiring pattern, the stepped portion can be flattened, and step breakage can be prevented when further semiconductor material is laminated on top of this. I can do it.

Further, this planarization makes it easier to perform photoetching on the surface of the semiconductor substrate afterward, making it easier to carry out microfabrication.

[Embodiments of the invention]

FIG. 3 shows a cross section of a main part of an embodiment of the present invention. 1
1 is an S1 substrate on which an element region is formed;
In this example, three wiring layers 131 to 13 are formed parallel to each other and adjacent to each other with the film 12 in between. Membrane 12 to Sl
For example, the thickness is 1.5 tones, and a concavo-convex pattern with a steep step of about the IP groove is formed on its surface corresponding to the wiring pattern, and the three wiring layers 131 to 13s are thinner than the concave-convex step. With the same conductor film, the middle wiring layer 1
The wiring layers 13r and 13m on both sides are arranged in the convex part and the three layers are disposed in the concave part. The horizontal distance between wiring layers 13s-1h is approximately zero.

With such a wiring structure, the capacitance associated with one wiring layer is extremely small, as is clear from the comparison with Figure 1.
It can be seen that since the separation distance is approximately zero, a significant increase in integration can be achieved by increasing the wiring density.

Next, an example of the method of the present invention will be described in 1. Figure 4(a)-(
d) Explain using t-. First, an element region is formed on the 981 substrate 31 810. The film 32 is formed to a thickness of approximately 3.0 μm, and 5 to Il! There is a step difference on the 320 surface of about 1
Form a pm recess. In this case, the recess is this 810
This corresponds to the middle wiring pattern among the three parallel wiring layers formed on 38132. After that, a phosphorus-doped polycrystalline silicon film 33 with a thickness of about 500 OA is applied to the entire surface by CVD.
Then, on top of that, as a mask material, about 510mm [34t 1.0μ solution] is deposited by the plasma method.
). After this, the entire surface was etched using NH4,
8) Mountains for selectively etching away the stepped portions of the IQl film 34) 1. 810. by plasma CVD method. The membrane 34 is NH
For 4PK, since the etching speed at the stepped portion is about 20 times that at the flat portion, only the stepped portion can be removed by etching the entire surface. Then, the polysilicon film 33 is selectively oxidized by the combustion (900° C., 100 minutes) oxidation method of hydrogen gas and oxygen gas using the remaining StO film 34 as an i-splash, so that the polysilicon haze at the stepped portion is removed. 1-1 1133f) 4til □. □I,. 61°1. The volume of the silicide film increases to about twice that of the polysilicon film. For this reason, a recess with a dimension that is four times or less the thickness of the polysilicon film is formed between the polysilicon 1133 and sio at the bottom of the recess.
It is completely buried with the thermal oxide film 35 of the film 34. In the case of a recess having a dimension more than four times the thickness of the polysilicon film, the angle of the recess is equal to that of the thermal oxide film 35.

The membrane 34 allows the angle to be more gradual than vertical.

For further flattening, for example, low viscosity (about 8 cp)
Photoresist) 36 t Apply to the entire surface of the semiconductor using a spinner at 6000 rpm to smooth the surface of the semiconductor.

After that, reactive ion etching RIE containing CF”at
photoresist 36, thermal oxide film 35 and 5IQl film 34.
Etching conditions CF4 where the etching rate becomes the same
Etching is performed using 50 cc Anin and a pressure of 30 mTorr.

When the polysilicon film 33 of the convex portion is exposed to the surface, RI
After finishing E, the remaining photoresist 361) sν
Remove everything with a tweezers. (d) According to this embodiment, by utilizing the conventional phosphorography technique No. 11, it is possible to reduce the capacitance between wiring layers and realize high-density wiring without performing difficult microfabrication. Particularly when applied to a large-scale integrated circuit with a large wiring area, such as a CPU, the effects of reduced chip area, higher integration, and higher reliability can be obtained.

In addition, since the semiconductor surface is flat, it is possible to prevent disconnections when layering insulating films and other materials that tend to cause disconnections, making it easier to create multilayer interconnects. Since there is no difference, it is easier to form a photoresist pattern.
Fine processing such as reducing f can be easily performed.

Although polycrystalline silicon is used as the conductor film in this embodiment, metals such as At, Muz-st, and W, and various metal norides may also be used. In addition, an 8-10m film made by the plus-t CVD method was used as a mask material.
If the etching rate at the stepped portion is higher than that at the flat portion, it can be used as a similar mask material. Specifically, 8i0 porphyrin obtained by the Sunoshitsuta method is suitable.

The method of selectively converting # when using metals such as AA is as follows:
There are methods such as anodic oxidation.

FIG. 5 shows a case of two-layer wiring as an embodiment of the present invention. 45 and 48 are interlayer insulating films, and 47 is an insulating film for planarization. First layer conductor film 43 and second layer conductor 8
46 is flattened by the 8101 film 44, so that mutually free wiring patterns and shapes are formed. Therefore, this method is particularly effective when forming a pattern in which the first and second conductor films are perpendicular to each other.

Next, an embodiment of the method of the present invention will be described using FIGS. 6(a) to 6(e). First, an element region is formed on the Sl substrate 5.
A Si false layer film 52 is formed on the 5iOFNI 52 to a thickness of about 2Pws, and a recess with a step height of about 1-N4 is formed on one surface of the 5iOFNI 52 by reactive ion etching using a photoresist as a mask. In this case, the recess corresponds to the middle wiring pattern among the three parallel wiring layers formed on the 5iOslE52. Thereafter, a phosphorus-doped polycrystalline silicon film 33 with a thickness of about 4000 Å is deposited on the entire surface by CVD, and a SiN film (54)' with a thickness of about 50 OA is deposited thereon.

2 and 5 as a mask material by plasma CVD method.
iOJJ(55'k 5000A &I[Mtlllt
T le...? After -O, the entire surface was etched using NH/i, and Sio! The film 54 is selectively removed by etching. The etching rate of the Si film 55 formed by the plasma CVD method at the stepped portion is about 20 times that of the flat portion compared to NH4F, so that only the stepped portion can be removed by etching the entire surface. Then, using the remaining Si (hg 55k mask), the SiN film 5 film tube 4 at the stepped portion is removed by chemical dry etching. After that, using the SiN film 54 as a mask, the polycrystalline silicon film 33 at the stepped portion is steam oxidized. Thermal oxidation is changed to 11 [56] by (& figure) Next, sto
w membrane +115.56. The SiN film 54t is removed so that the polycrystalline silicon film 33 is not exposed. After that, the polycrystalline silicon film 53 and gold are selectively patterned using photolithography (photolithography), (Figure b), for example, t Jd cvo -s
lo1 film 57't-1, 5'μm1 maotoresist t
The semiconductor surface is planarized by stacking layers of about 1.0 μm, and the CCVD-8lo film 57 is planarized using RIK.
Figure) When using this method, the conductor film 53t is removed before flattening.
- Since patterning can be performed freely, it is possible to diversify wiring patterns.

Further, since selective oxidation is performed on the thin SiN film 54t-mask, selective oxidation can be performed in minute recesses, and dimensional control can be easily performed, leading to improved yield.

In the above embodiment, the selective oxidation may be performed after removing the StO film 55t, the polycrystalline silicon film 53& may be patterned while the thermal oxide film 56 remains, or the polycrystalline silicon film 53& may be further patterned. In some cases, it is easier to flatten the area if it is left in place.

Further, even in the case where the conductor film remaining on the flat part is left as a shield film after the wiring pattern is separated by uneven step portions, the subsequent PEP step can be similarly omitted.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the wiring structure of a conventional semiconductor device, Figure 2 is a diagram showing the relationship between the wiring width and capacitance, and Figure 3 (
4# flaw is a diagram showing the wiring structure of one embodiment of the present invention, FIG. 4 is a diagram showing the manufacturing process of one embodiment of the present invention, and FIGS. 5 and 6 (a) to (e) are It is the ninth figure explaining the manufacturing process of one Example of the method of this invention. In the figure, 1.11, 31, 41.51...Semiconductor substrate (St) 2
．． 12, 32, 42, 45, 48.52... interlayer separation i
#! , membrane (S103) 3.13, 33, 43, 46.5
3... Conductive film (polycrystalline silicon film) 34.55.
...Plasma 5iO1 (mask material) 54 ...Si
N (z) 35.56...Thermal oxide film 47.57...Insulating film for planarization (7317) 41 patent attorneys Norichika Kensuke (and 1 other person) Figure 1 Figure 2 Bar W (= S) Figure 3, Figure 4, Figure 4, Figure 5, Figure 6

Claims (4)

[Claims] (1) In a semiconductor device in which a wiring layer is provided on a semiconductor substrate on which an element region is formed, with an insulating film interposed therebetween, the wiring layer is formed using the same conductive film forming process and has portions adjacent to each other in parallel. a step of forming an insulating film and forming irregularities corresponding to a wiring pattern on its surface; a step of depositing a conductive film over the entire surface of the insulating film; and a step of etching a mask material with a high etching rate at stepped portions over the entire surface of the conductor film. A step of selectively removing the mask material at the step portions of the unevenness by depositing and etching the entire surface, and using the remaining mask material to transform the conductive film at the step portions into an insulating film and removing the mask material from the step portions of the unevenness. 1. A method of manufacturing a semiconductor device comprising: forming interconnection layers adjacent to each other in parallel and separated by a step portion. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the method for transforming the conductor film into an insulating film is to transform the conductor into an oxide film by oxidizing the conductor. . (3) When the conductor film is transformed into an insulating film, the volume of the insulating film is formed to be larger than the volume of the conductor before the transformation, and some of the irregularities are buried. ,
A method for manufacturing a semiconductor device according to a patent, characterized in that it includes a step of making the uneven portions flatter than when etched with gold. (4) The method for manufacturing a semiconductor device according to claim 3, further comprising the step of, after forming the altered insulating film, filling the concave portion of the uneven portion with one or more layers of insulating film and planarizing it.