JPS5893326A - マスク位置合せ測定用マ−ク - Google Patents
マスク位置合せ測定用マ−クInfo
- Publication number
- JPS5893326A JPS5893326A JP57143550A JP14355082A JPS5893326A JP S5893326 A JPS5893326 A JP S5893326A JP 57143550 A JP57143550 A JP 57143550A JP 14355082 A JP14355082 A JP 14355082A JP S5893326 A JPS5893326 A JP S5893326A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- layer
- level
- conductive
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10P74/277—
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- H10P74/203—
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Engineering & Computer Science (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Manufacturing & Machinery (AREA)
- Automation & Control Theory (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US325942 | 1981-11-30 | ||
| US06/325,942 US4399205A (en) | 1981-11-30 | 1981-11-30 | Method and apparatus for determining photomask alignment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893326A true JPS5893326A (ja) | 1983-06-03 |
| JPS6253946B2 JPS6253946B2 (cg-RX-API-DMAC10.html) | 1987-11-12 |
Family
ID=23270099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57143550A Granted JPS5893326A (ja) | 1981-11-30 | 1982-08-20 | マスク位置合せ測定用マ−ク |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4399205A (cg-RX-API-DMAC10.html) |
| EP (1) | EP0080619B1 (cg-RX-API-DMAC10.html) |
| JP (1) | JPS5893326A (cg-RX-API-DMAC10.html) |
| DE (1) | DE3279615D1 (cg-RX-API-DMAC10.html) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4672314A (en) * | 1985-04-12 | 1987-06-09 | Rca Corporation | Comprehensive semiconductor test structure |
| IT1186523B (it) * | 1985-12-31 | 1987-11-26 | Sgs Microelettronica Spa | Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore |
| US5109430A (en) * | 1986-07-22 | 1992-04-28 | Schlumberger Technologies, Inc. | Mask alignment and measurement of critical dimensions in integrated circuits |
| US4965842A (en) * | 1986-07-22 | 1990-10-23 | Schlumberger Technologies, Inc. | Method and apparatus for measuring feature dimensions using controlled dark-field illumination |
| US4918377A (en) * | 1988-12-05 | 1990-04-17 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Integrated circuit reliability testing |
| US5044750A (en) * | 1990-08-13 | 1991-09-03 | National Semiconductor Corporation | Method for checking lithography critical dimensions |
| ES2042382B1 (es) * | 1991-10-30 | 1996-04-01 | Consejo Superior Investigacion | Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular |
| IT1252539B (it) * | 1991-12-18 | 1995-06-19 | St Microelectronics Srl | Procedimento per la realizzazione di strutture metrologiche particolarmente per la misura diretta di errori introdotti da sistemi di allineamento. |
| US5373232A (en) * | 1992-03-13 | 1994-12-13 | The United States Of America As Represented By The Secretary Of Commerce | Method of and articles for accurately determining relative positions of lithographic artifacts |
| JP3363082B2 (ja) * | 1997-12-05 | 2003-01-07 | 株式会社東芝 | パターンの合わせずれの電気的測定方法 |
| US6716559B2 (en) | 2001-12-13 | 2004-04-06 | International Business Machines Corporation | Method and system for determining overlay tolerance |
| US6620635B2 (en) | 2002-02-20 | 2003-09-16 | International Business Machines Corporation | Damascene resistor and method for measuring the width of same |
| US7084427B2 (en) | 2003-06-10 | 2006-08-01 | International Business Machines Corporation | Systems and methods for overlay shift determination |
| JP2005285308A (ja) * | 2004-03-02 | 2005-10-13 | Tdk Corp | 薄膜処理方法及び薄膜磁気ヘッドの製造方法 |
| JP2008244254A (ja) * | 2007-03-28 | 2008-10-09 | Fujitsu Microelectronics Ltd | 半導体装置とその製造方法、及び分割露光用マスク |
| US9252202B2 (en) * | 2011-08-23 | 2016-02-02 | Wafertech, Llc | Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement |
| KR102721980B1 (ko) | 2022-02-24 | 2024-10-25 | 삼성전자주식회사 | 기판 정렬 장치 및 이를 이용한 기판 정렬 방법 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52113768A (en) * | 1976-03-22 | 1977-09-24 | Hitachi Ltd | Mask matching shift measuring pattern |
| JPS5728573A (en) * | 1980-07-24 | 1982-02-16 | Toshiba Corp | Controlling method of multiplied inverter |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3482977A (en) * | 1966-02-11 | 1969-12-09 | Sylvania Electric Prod | Method of forming adherent masks on oxide coated semiconductor bodies |
| US3808527A (en) * | 1973-06-28 | 1974-04-30 | Ibm | Alignment determining system |
| US3849136A (en) * | 1973-07-31 | 1974-11-19 | Ibm | Masking of deposited thin films by use of a masking layer photoresist composite |
| US3974443A (en) * | 1975-01-02 | 1976-08-10 | International Business Machines Corporation | Conductive line width and resistivity measuring system |
| US4024561A (en) * | 1976-04-01 | 1977-05-17 | International Business Machines Corporation | Field effect transistor monitors |
| FR2473789A1 (fr) * | 1980-01-09 | 1981-07-17 | Ibm France | Procedes et structures de test pour circuits integres a semi-conducteurs permettant la determination electrique de certaines tolerances lors des etapes photolithographiques. |
-
1981
- 1981-11-30 US US06/325,942 patent/US4399205A/en not_active Expired - Lifetime
-
1982
- 1982-08-20 JP JP57143550A patent/JPS5893326A/ja active Granted
- 1982-11-10 DE DE8282110347T patent/DE3279615D1/de not_active Expired
- 1982-11-10 EP EP82110347A patent/EP0080619B1/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52113768A (en) * | 1976-03-22 | 1977-09-24 | Hitachi Ltd | Mask matching shift measuring pattern |
| JPS5728573A (en) * | 1980-07-24 | 1982-02-16 | Toshiba Corp | Controlling method of multiplied inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0080619A3 (en) | 1986-01-08 |
| DE3279615D1 (en) | 1989-05-18 |
| EP0080619B1 (en) | 1989-04-12 |
| EP0080619A2 (en) | 1983-06-08 |
| US4399205A (en) | 1983-08-16 |
| JPS6253946B2 (cg-RX-API-DMAC10.html) | 1987-11-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5893326A (ja) | マスク位置合せ測定用マ−ク | |
| US4347479A (en) | Test methods and structures for semiconductor integrated circuits for electrically determining certain tolerances during the photolithographic steps | |
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