DE3279615D1 - Method for determining photomask alignment - Google Patents

Method for determining photomask alignment

Info

Publication number
DE3279615D1
DE3279615D1 DE8282110347T DE3279615T DE3279615D1 DE 3279615 D1 DE3279615 D1 DE 3279615D1 DE 8282110347 T DE8282110347 T DE 8282110347T DE 3279615 T DE3279615 T DE 3279615T DE 3279615 D1 DE3279615 D1 DE 3279615D1
Authority
DE
Germany
Prior art keywords
photomask alignment
determining
determining photomask
alignment
photomask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282110347T
Other languages
German (de)
English (en)
Inventor
Albert Stephen Bergendahl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3279615D1 publication Critical patent/DE3279615D1/de
Expired legal-status Critical Current

Links

Classifications

    • H10P74/277—
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H10P74/203—

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE8282110347T 1981-11-30 1982-11-10 Method for determining photomask alignment Expired DE3279615D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/325,942 US4399205A (en) 1981-11-30 1981-11-30 Method and apparatus for determining photomask alignment

Publications (1)

Publication Number Publication Date
DE3279615D1 true DE3279615D1 (en) 1989-05-18

Family

ID=23270099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282110347T Expired DE3279615D1 (en) 1981-11-30 1982-11-10 Method for determining photomask alignment

Country Status (4)

Country Link
US (1) US4399205A (cg-RX-API-DMAC10.html)
EP (1) EP0080619B1 (cg-RX-API-DMAC10.html)
JP (1) JPS5893326A (cg-RX-API-DMAC10.html)
DE (1) DE3279615D1 (cg-RX-API-DMAC10.html)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672314A (en) * 1985-04-12 1987-06-09 Rca Corporation Comprehensive semiconductor test structure
IT1186523B (it) * 1985-12-31 1987-11-26 Sgs Microelettronica Spa Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore
US4965842A (en) * 1986-07-22 1990-10-23 Schlumberger Technologies, Inc. Method and apparatus for measuring feature dimensions using controlled dark-field illumination
US5109430A (en) * 1986-07-22 1992-04-28 Schlumberger Technologies, Inc. Mask alignment and measurement of critical dimensions in integrated circuits
US4918377A (en) * 1988-12-05 1990-04-17 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Integrated circuit reliability testing
US5044750A (en) * 1990-08-13 1991-09-03 National Semiconductor Corporation Method for checking lithography critical dimensions
ES2042382B1 (es) * 1991-10-30 1996-04-01 Consejo Superior Investigacion Estructura de test para la medida del desalineamiento entre niveles en tecnologias microelectronicas, basada en transistores mos con puerta triangular
IT1252539B (it) * 1991-12-18 1995-06-19 St Microelectronics Srl Procedimento per la realizzazione di strutture metrologiche particolarmente per la misura diretta di errori introdotti da sistemi di allineamento.
US5373232A (en) * 1992-03-13 1994-12-13 The United States Of America As Represented By The Secretary Of Commerce Method of and articles for accurately determining relative positions of lithographic artifacts
JP3363082B2 (ja) * 1997-12-05 2003-01-07 株式会社東芝 パターンの合わせずれの電気的測定方法
US6716559B2 (en) 2001-12-13 2004-04-06 International Business Machines Corporation Method and system for determining overlay tolerance
US6620635B2 (en) * 2002-02-20 2003-09-16 International Business Machines Corporation Damascene resistor and method for measuring the width of same
US7084427B2 (en) 2003-06-10 2006-08-01 International Business Machines Corporation Systems and methods for overlay shift determination
JP2005285308A (ja) * 2004-03-02 2005-10-13 Tdk Corp 薄膜処理方法及び薄膜磁気ヘッドの製造方法
JP2008244254A (ja) * 2007-03-28 2008-10-09 Fujitsu Microelectronics Ltd 半導体装置とその製造方法、及び分割露光用マスク
US9252202B2 (en) * 2011-08-23 2016-02-02 Wafertech, Llc Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement
KR102721980B1 (ko) 2022-02-24 2024-10-25 삼성전자주식회사 기판 정렬 장치 및 이를 이용한 기판 정렬 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3482977A (en) * 1966-02-11 1969-12-09 Sylvania Electric Prod Method of forming adherent masks on oxide coated semiconductor bodies
US3808527A (en) * 1973-06-28 1974-04-30 Ibm Alignment determining system
US3849136A (en) * 1973-07-31 1974-11-19 Ibm Masking of deposited thin films by use of a masking layer photoresist composite
US3974443A (en) * 1975-01-02 1976-08-10 International Business Machines Corporation Conductive line width and resistivity measuring system
JPS52113768A (en) * 1976-03-22 1977-09-24 Hitachi Ltd Mask matching shift measuring pattern
US4024561A (en) * 1976-04-01 1977-05-17 International Business Machines Corporation Field effect transistor monitors
FR2473789A1 (fr) * 1980-01-09 1981-07-17 Ibm France Procedes et structures de test pour circuits integres a semi-conducteurs permettant la determination electrique de certaines tolerances lors des etapes photolithographiques.
JPS5728573A (en) * 1980-07-24 1982-02-16 Toshiba Corp Controlling method of multiplied inverter

Also Published As

Publication number Publication date
US4399205A (en) 1983-08-16
EP0080619A2 (en) 1983-06-08
EP0080619B1 (en) 1989-04-12
JPS5893326A (ja) 1983-06-03
JPS6253946B2 (cg-RX-API-DMAC10.html) 1987-11-12
EP0080619A3 (en) 1986-01-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee