JPS5892042A - Interruption processor - Google Patents

Interruption processor

Info

Publication number
JPS5892042A
JPS5892042A JP19029881A JP19029881A JPS5892042A JP S5892042 A JPS5892042 A JP S5892042A JP 19029881 A JP19029881 A JP 19029881A JP 19029881 A JP19029881 A JP 19029881A JP S5892042 A JPS5892042 A JP S5892042A
Authority
JP
Japan
Prior art keywords
interrupt
circuit
request
signal
interrupt request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19029881A
Other languages
Japanese (ja)
Inventor
Hiroshi Matsumoto
松元　博司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP19029881A priority Critical patent/JPS5892042A/en
Publication of JPS5892042A publication Critical patent/JPS5892042A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To avoid the interruption request of an interruption request circuit from being affected due to a failure of other interruption request circuit, by outputting an interruption request with a time division system and multiple- connecting connection signal lines between a request circuit and a discriminating circuit to a plurality of request circuits. CONSTITUTION:An interruption request signal 6A is generated at an interruption request circuit 3A and a time division interruption generating circuit 13A is started. The circuit 13A outputs an interruption signal to a time division interruption signal line 14 at an assigned time in advance and the signal is inputted to an interruption request discriminating circuit 12. The circuit 12 discriminates the circuit 13A having the interruption request from the time of an outputted signal on the signal line 14 and outputs a corresponding discrimination signal 11A. Similarly, when a request signal 6B generated at an interruption request circuit 3B, a discrimination signal 11B is outputted from the circuit 12 and when a request signal 6C is generated from a request circuit 3C, then a discrimination signal 11C is outputted from the circuit 12 similarly.

Description

【発明の詳細な説明】 本発明は複数の割込要求信号を受付けて割込処理１行な
う割込処理装置に関し、特に時分割処理によ〉割込要求
を判別し接続信号を簡潔にした割込処理装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt processing device that accepts multiple interrupt request signals and performs one interrupt process, and in particular, an interrupt processing device that discriminates interrupt requests and simplifies connection signals by time-sharing processing. This relates to a processing device.

従来のこの種の割込処理は第１図に示す様な構成でなさ
れる。処理受付回Ｗ＆ｌに処理を要求する割込要求回路
３Ａ、３Ｂ及び３Ｃが割込要求信号６人、６Ｂ及び６Ｃ
からそれぞれの割込発生回路４Ａ、４Ｂ及び４Ｃｔ−通
して割込信号７にて処理受付回路ｌに割込要求する。処
理受付回路１にて割込みが受付けられると、割込受付信
号８人が処理受付回Ｗ＆ｌより割込発生回路４人に、割
込発生回路４人から割込受付信号８Ｂが割込発生回路４
Ｂに、又、割込発生回＃６４Ｂから割込受付信号８Ｃが
割込受付信号８Ｃが割込発生回路４Ｃに送出され、処理
を要求し友割込要求回路３Ａ、３Ｂ又は３Ｃでは、処理
応答信号９Ａ、９Ｂ又は９Ｃが割込発生回路４Ａ、４Ｂ
又は４Ｃより処理応等回路５Ａ、１５Ｊ　　５ｃのいず
れか一つに送出され、さらに要求回路信号１０が処理応
答回Ｍ５Ａ、　　５Ｂ又は５Ｃよ〕要求判別口ｗｒ２に
送出され、どの割込要求回路よシ処理要求があり几かを
判別する。Conventional interrupt processing of this type is performed with a configuration as shown in FIG. Interrupt request circuits 3A, 3B, and 3C that request processing from the processing reception circuit W&l send interrupt request signals 6, 6B, and 6C.
An interrupt request is made to the processing reception circuit 1 by an interrupt signal 7 through the respective interrupt generation circuits 4A, 4B and 4Ct. When an interrupt is accepted by the processing reception circuit 1, the interrupt reception signal 8 is sent from the processing reception circuit W&l to the 4 interrupt generation circuits, and the interrupt reception signal 8B from the 4 interrupt generation circuits is sent to the interrupt generation circuit 4.
Also, from the interrupt occurrence time #64B, the interrupt acceptance signal 8C is sent to the interrupt generation circuit 4C to request processing, and the friend interrupt request circuit 3A, 3B or 3C performs the processing Response signal 9A, 9B or 9C is sent to interrupt generation circuit 4A, 4B
Or, the request circuit signal 10 is sent from the processing response circuit M5A, 5B or 5C to one of the processing response circuits 5A, 15J, and 5c from the processing response circuit M5A, 5B, or 5C. Determine whether there is a processing request.

しかしながら、この種の割込処理装置では、割込要求回
路間の接続が有る為、接続線が複雑になｐ、又、割込要
求回路を増設、削除、変更する時、ｇ！続■の変更が必
要にな〉、さらに割込要求回路ＯＷ！４続が直列である
光め、前段の割込要求回路の故障によ１）ｆｌｋＲの割
込要求回路の割込要求ができなくなる欠点を有してい喪
。However, in this type of interrupt processing device, since there are connections between interrupt request circuits, the connection lines become complicated.Also, when adding, deleting, or changing interrupt request circuits, g! It is necessary to make the following changes>, and the interrupt request circuit OW! I'm saddened that the four-connected light circuit has the disadvantage that 1) the flkR interrupt request circuit cannot issue an interrupt request due to a failure of the interrupt request circuit in the previous stage.

本発明の目的はこの従来装置の欠点を解決する九めに、
割込要求回路に時分割多重方式の処理によ〉割込信号を
発生する割込発生回路を設け、複数の割込要求回路と、
割込要求判別回路間の接続をマルチ接続にして割込処理
を行なうようにした割込処理装置を提供することにある
。A ninth object of the present invention is to solve the drawbacks of this conventional device.
The interrupt request circuit is provided with an interrupt generation circuit that generates an interrupt signal by time division multiplexing processing, and a plurality of interrupt request circuits,
An object of the present invention is to provide an interrupt processing device which performs interrupt processing by making multiple connections between interrupt request determination circuits.

すなわち本発明によれば演算処理装置等へ割込信号を送
出する際、その前処理部として、複数の割込要求信号を
受付けて割込処理を行なう割込処理装置において、割込
要求信号を受付は所定の時分割割込データ配列に変換す
る複数の割込要求回路群と、前記割込要求回路群の時分
割割込データ出力端をマルチ接続して入力し、前記時分
割割込データがどの割込要求回路から出力され九もので
あるかを判別する割込要求判別回路とを含み、複数の割
込要求信号を時分割にて処理することを特徴とする割込
処理装置が得られる。。That is, according to the present invention, when an interrupt signal is sent to an arithmetic processing device or the like, an interrupt processing device that receives a plurality of interrupt request signals and performs interrupt processing serves as a preprocessing section for transmitting the interrupt request signal. The reception is performed by inputting multiple interrupt request circuit groups that convert into a predetermined time-sharing interrupt data array and the time-sharing interrupt data output terminals of the interrupt request circuit groups, and inputting the time-sharing interrupt data. An interrupt processing device is provided, which includes an interrupt request determination circuit that determines which interrupt request circuit outputs an interrupt request signal, and processes a plurality of interrupt request signals in a time-sharing manner. It will be done. .

次に本発明の一実Ｍ例を図面を参照して説明する。Next, an example M of the present invention will be explained with reference to the drawings.

第２図は本発明の一実＊ＩＰｇｔ−示すブロック図であ
って、割込による処理を要求する割込要求信号６人、６
ｎ、５３ｃで起動され時分割で割込信号を発生する時分
割割込発生口Ｍ１３Ａ、１３Ｂ及び１３Ｃおよび割込要
求信号６人、６Ｂ、６Ｃの発生源を持つ複数の割込要求
回路３人、３Ｂ及び３Ｃと、便数の時分割割込発生回路
１３Ａ、１３Ｂ。FIG. 2 is a block diagram showing one aspect of the present invention *IPgt-, in which interrupt request signals requesting processing by interrupt, 6 people, 6
time-sharing interrupt generation ports M13A, 13B, and 13C that are activated by time-sharing interrupt signals M13A, 53c, and 6 interrupt request signal sources, and 3 multiple interrupt request circuits that have generation sources of 6B and 6C; , 3B and 3C, and time division interrupt generation circuits 13A and 13B for the number of flights.

１３Ｃで発生され九割込信号を時分割多重方式で伝送す
る一本の時分割割込データ１４と、一本の時分割割込信
号１１１４から複数の割込要求回路３Ａ、３Ｂ、３ｃか
らの割込要求を入力し、割込要求元を判別し該当する判
別信号１１Ａ、ＩＩＢ。One time-division interrupt data 14 that transmits nine interrupt signals generated by the time-division multiplexing system 1114, and one time-division interrupt signal 1114 from a plurality of interrupt request circuits 3A, 3B, and 3c. An interrupt request is input, the interrupt request source is determined, and the corresponding determination signal 11A, IIB.

１１Ｃのいずれか會出力する割込要求判別回路１２とｔ
含む。11C, the interrupt request determination circuit 12 and t
include.

次にこの回路の動作を順を追りて説明する。＠込要求回
路３人で割込要求信号６人が発生すると割込要求信号６
人は時分割割込発生口１２）１３Ａｔ起動する０時分割
割込発生回路１３Ａはあらかじめ割ヤあてられ九時間に
時分割割込信号１１１４に割込信号を出力し、割込要求
回路回ｉ！１２に入力される０割込要求判別回ｖ６１２
は時分割割込信号１１１４に出力された信号の時間から
割込要求のある割込要求回路１３Ａｔ−判別し該当する
判別信号１１人金山力する。Next, the operation of this circuit will be explained step by step. @Interrupt request circuit When interrupt request signal 6 is generated by 3 people, interrupt request signal 6 is generated.
The time-sharing interrupt generation circuit 13A is assigned a time slot in advance and outputs an interrupt signal to the time-sharing interrupt signal 1114 at the 9th hour, and the interrupt request circuit 12) 13At starts. ! 0 interrupt request determination time input to 12 v612
The interrupt request circuit 13At which has an interrupt request is determined based on the time of the signal outputted as the time division interrupt signal 1114, and the corresponding determination signal 11 is sent.

同様に割込要求回路３Ｂで割込要求信号６Ｂが発生した
時は、判別信号１１Ｂが、割込要求回路３Ｃで割込要求
信号６Ｃが発生し九時は判別信号１１Ｃがそれぞれ割込
要求判別回路１２から出力する。Similarly, when the interrupt request signal 6B is generated in the interrupt request circuit 3B, the determination signal 11B is generated, the interrupt request signal 6C is generated in the interrupt request circuit 3C, and the determination signal 11C is used to determine the interrupt request. Output from circuit 12.

本発明は以上説明したように、割込要求を時分割方式で
割込信号−に出力する割込発生口＊’ｒ設け、割込要求
回路と割込要求判別回路間の接続信号線管複数の割込要
求回路にマルチ接読された時分割割込信号層で構成する
ことにより割込要求回路間の接続信号を簡潔にする効果
があるばかｐか、さらに一つの割込要求回路の故障によ
〉他の割込要求回路の割込要求が影響されないようにで
きるという効果ｔＴｏる。As explained above, the present invention provides an interrupt generation port*'r for outputting an interrupt request as an interrupt signal in a time-sharing manner, and a plurality of connection signal lines between an interrupt request circuit and an interrupt request determination circuit. It is possible to simplify the connection signals between interrupt request circuits by configuring the time-division interrupt signal layer that is read multiple times to the interrupt request circuit, or if one interrupt request circuit fails. This has the effect that interrupt requests of other interrupt request circuits can be prevented from being affected.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の割込処理装置を示すブロック図、第２図
は本発明による実ＩＩ例會示すブロック図でめる。 なお図において、１・・・・・・処理受付回路、２・・
・・・・要求判別回路、３Ａ、３Ｂ及び３Ｃ・・・・・
・割込要求回路、４人、４Ｂ及び４Ｃ・・・・・・割込
発生回路、５Ａ、５Ｂ及び５Ｃ・・・・・・処理応答回
路、６人、６Ｂ及び６Ｃ・・・・・・割込要求信号、７
・・・・・・割込信号、８Ａ、８Ｂ及び８Ｃ・・・・・
・割込受付信号、９Ａ、９１３及び９Ｃ・・・・・・処
理応答回路、１０・・・・・・要求回路信号、１１人、
１１Ｂ及び１１Ｃ・・・・・・判別信号、１２・・・・
・・割込要求′判別回路、１３人、１３Ｂ及び′　　１
３Ｃ・・・・・・時分割割込発生回路、１４・・・・・
・時分割割込データである。 Ｙ・１反 第２ソFIG. 1 is a block diagram showing a conventional interrupt processing device, and FIG. 2 is a block diagram showing a second embodiment of the present invention. In the figure, 1... processing reception circuit, 2...
...Request discrimination circuit, 3A, 3B and 3C...
- Interrupt request circuit, 4 people, 4B and 4C...Interrupt generation circuit, 5A, 5B and 5C...Processing response circuit, 6 people, 6B and 6C... Interrupt request signal, 7
...Interrupt signal, 8A, 8B and 8C...
・Interrupt reception signal, 9A, 913 and 9C...Processing response circuit, 10...Request circuit signal, 11 people,
11B and 11C...Discrimination signal, 12...
...Interrupt request 'discrimination circuit, 13 people, 13B and '1
3C...Time division interrupt generation circuit, 14...
・This is time-sharing interrupt data. Y・1 anti 2nd so

Claims (1)

【特許請求の範囲】[Claims] 込要求１号を受付けて割込処理１行なう割込処理装置に
おいて、割込要求信号を受付は所定の時分割割込データ
に変換する複数の割込要求回路群と、前記割込要求回路
群の時分割割込データ出力端をマルチ接続して入力し、
前記時分割割込データが前記割込要求回路のうち、いず
れから出力され九ものであるかを判別する割込要求判別
回路とを含み、複数の割込要求信号を時分割にて処理す
ることを特徴とする割込部１装置。An interrupt processing device that accepts a first interrupt request and performs one interrupt process includes a plurality of interrupt request circuit groups that convert the interrupt request signal into predetermined time-sharing interrupt data; and the interrupt request circuit group. Multi-connect and input the time-sharing interrupt data output terminals of
and an interrupt request determination circuit that determines which of the interrupt request circuits the time-sharing interrupt data is output from, and processes a plurality of interrupt request signals in a time-sharing manner. An interrupt unit 1 device characterized by:
JP19029881A 1981-11-27 1981-11-27 Interruption processor Pending JPS5892042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19029881A JPS5892042A (en) 1981-11-27 1981-11-27 Interruption processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19029881A JPS5892042A (en) 1981-11-27 1981-11-27 Interruption processor

Publications (1)

Publication Number Publication Date
JPS5892042A true JPS5892042A (en) 1983-06-01

Family

ID=16255832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19029881A Pending JPS5892042A (en) 1981-11-27 1981-11-27 Interruption processor

Country Status (1)

Country Link
JP (1) JPS5892042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014241082A (en) * 2013-06-12 2014-12-25 Ｎｅｃエンジニアリング株式会社 Method for rescuing significant line in pattern wiring for achieving high density mounting and high density mounting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014241082A (en) * 2013-06-12 2014-12-25 Ｎｅｃエンジニアリング株式会社 Method for rescuing significant line in pattern wiring for achieving high density mounting and high density mounting device

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