JPH03105656A - Bus control system - Google Patents

Abstract

PURPOSE:To cope with plural bus evacuation requests by applying three signals of a bus evacuation request signal, a bus evacuation destination detecting strobe signal and a bus evacuation destination determining strobe signal. CONSTITUTION:The system is provided with a bus evacuation request signal line 14, a bus evacuation destination detecting stroke signal line 15, and a bus evacuation destination determining strobe signal line 16. Also, an intrinsic slave ID code is allocated to each slave S1 - Sn, respectively, and based on a signal for requesting a bus evacuation from a slave having a slave ID code conforming to a bus evacuation destination strobe signal outputted from a master M, the master gives a bus evacuation permitting signal to its slave. In such a way, it is possible to cope rationally with bus evacuation requests from plural slaves, and also, it is scarcely necessary to modify the existing bus system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 3] The present invention relates to a bus control system in a bus system such as a computer. This paper concerns a bus control method in a bus system configured to do so. (Prior Art) For example, in a computer bus system, one data bus managed by a master board Ij (hereinafter referred to as master) is shared by the master and a plurality of slave boards (hereinafter referred to as slaves). In addition, there is a system in which the data bus is used in a time-sharing manner. Figure 3 schematically shows a bus system configured in this way, where M is a master that manages the data bus DB, and S is a master that manages the data bus DB.
l~S. is n slaves, these masters M and n
slave S. -S. share one data bus DB. In this bus system, in order to use the data bus DB in a time-sharing manner, bus handover has conventionally been performed by controlling the bus as follows. That is, if one slave S wants to use the data bus DB, a signal requesting bus surrender (hereinafter referred to as H
(denoted as OLD) is sent to master M. This HO
Master M, which has received LD, sends back a bus handover permission signal (hereinafter referred to as HLDA) to slave S1.

When the slave S receives the HLDA, it learns that the data bus DB has been surrendered, and starts using the data bus DB. [Problems to be Solved by the Invention] However, in the conventional bus control method described above, when there is a request for bus surrender from a plurality of slaves, HOLD and HLDA are required for each slave S1 to Sll. In a bus system with only one pair of HLDAs, it is not possible to respond to multiple bus surrender requests. The present invention has been made with the above-mentioned considerations in mind, and its purpose is to be able to respond to multiple bus surrender requests while maintaining the conventional signal format, and to be able to handle multiple bus surrender requests while maintaining the conventional signal format. The purpose of this invention is to provide a bus control method that can rationally control a bus system configured such that one data bus is shared by a master and multiple slaves. [Means for Solving the Problems] In order to achieve the above-mentioned object, the bus control method according to the present invention includes a bus surrender request signal line to which a bus surrender request signal from a slave is output, and a bus surrender request signal line for outputting a bus surrender request signal from a slave. A bus surrender destination detection strobe signal line that is put into a strobe state based on the output of a handover request signal to the bus surrender request signal line, and a bus surrender destination to which a bus surrender destination determination strobe signal from the master is output. A determination strobe signal line is provided, a unique slave ID code is assigned to each slave, and when a bus surrender request signal is output from the slave, a bus surrender destination determination strobe signal is output from the master. The master is arranged to give a bus handover permission signal to the slave based on a signal requesting bus handover from a slave having a matching slave ID code. [Operation] According to the above structure, by simply adding three signals, the bus surrender request signal, the bus surrender destination detection strobe signal, and the bus surrender destination determination strobe signal, to the control signals in the conventional bus system. , bus surrender requests from multiple slaves can be handled rationally, and there is almost no need to modify the existing bus system. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the structure of a bus system for explaining the bus control method according to the present invention. In this figure, M is a master, and this master M and n slaves S1 to S,1
It has a function to manage a common data bus DB, and internally includes a slave ID code input circuit 1, a bus handover destination determination circuit 2, a slave ID code output circuit 3, and a slave ID code input circuit 1.
Code input/output control circuit 4, HOLD/HLDA
The bus transfer control circuit 5 is provided with a bus handover control circuit 5, etc.

In addition, the slaves S, ~S, l include, for example, a bus surrender request signal (hereinafter referred to as BRQ) output circuit 6, a slave L/-BL ID code output circuit 7, a slave ID code input latch circuit 8, and a HOLD output circuit. Circuit 9, HODA input circuit 1
0, a slave ID code setting circuit l1, etc. are provided, respectively.

L2 is a HOLD signal line, 13 is an HLDA signal line, l4 is a BRQ signal line, 15 is a bus handover destination detection strobe signal (hereinafter referred to as BPR) line,
16 is a bus handover destination determination strobe signal (hereinafter referred to as BPW).
), and these signal lines 12 to 16 are
It is provided on a mother board (hereinafter referred to as mother) together with the data bus DB. Now, the first slave S1 and the second slave S, (not shown)
We will explain the case where a bus surrender request occurs in that order. When a bus surrender request occurs in the slave, the signal is applied to the BRQ signal line 14 via the BRQ output circuit 6, but since the BRQ output circuit 6 is composed of an open collector type knot element, the BRQ signal line 14 is 14
becomes low level. Note that BRQ is wired-ORed on the mother, and BRQ is input to the master M via the slave 10 code input/output control circuit 4.
When the master M receives the BRQ, in order to detect which slave is requesting bus handover, the master M sets the data bus DB to the input state and sends the BPR via the slave ID code input/output control circuit 4. A pulse-like BPR (M) is output to the signal line l5. Then, each slave SI to S7 connects to the slave ID code setting circuit 11 within the period when the BPR signal line 15 is at a low level.
The respective slave 10 codes (low level signals corresponding to any bits of the data bus DB) are output to the 1-bit signal line of the data bus DB through the . Master M connects to data bus DB at the rising edge of BPH.
The contents of the slave ID code are taken in through the slave ID code input circuit 1, and the slave requesting bus handover is detected based on the low level bit therein. Then, the master M selects one of these slaves using the bus handover destination determination circuit 2, and outputs the slave ID code (a low-level signal output to any bit of the data bus) corresponding to the selected slave. At the same time, a pulse-like B P W (M) is output to the BPW signal line 16 via the slave ID code input/output control circuit 4. Each slave S,−
S. latches the bit information of the data bus DB corresponding to each slave SI to S3 in the slave ID code input latch circuit 8 at the rising edge of BPW. The slave ID code input latch circuit 8 is connected to the same signal line as the bit of the data bus DB that outputs the low level slave ID code during the period when the BPR signal line 15 is low level, and the master M If it is the selected slave, the slave 10 code (low level) can be latched. And the slave [
) The slave that latched the code recognizes that it has acquired the right to use the bus, and outputs HO via the OLD output circuit 9.
Outputs low-level HOLD to LD fK line 12 to request master M to surrender the bus.HOLD/
The master M receives the HOLD via the bus handover control circuit 5 using the HLDA, and transfers the data bus DB.
At the same time, HLDA is set to low level via the circuit 5. The slave can use the data bus DB from the moment HLDA becomes low level. Note that if a slave that has acquired the right to use the bus relinquishes that right, the slave will use BRQ and 1{O
Set LD to high level and remove these. At this time, if the other slaves are outputting BRQ (low level), BRQ is wired-ORed on the mother, so master M is continuously requested to hand over the bus. Then, the slave requesting bus handover is detected by BPR and BPW using the procedure described above. FIG. 2 shows, for example, BRQ+ (see (a)) and BRQI from the first slave S1 and the second slave S, in that order.
BR Q (see (c)) input to master M when (see (b)) is output, B P R (see (di)) and BPW (
(see (e)), I{
OLD I (see (f)}, HOLD2 output from second slave S3 (see (8)), HOLD input to master M (see (b)), HLDA output from master M (( i)), the slave ID code in the data bus DB (see (j)), and the bus user (see (j)).
(see (g))). [Effects of the Invention] As explained above, according to the present invention, a bus surrender request signal, a bus surrender request signal, a control signal in a conventional bus system,
By simply adding three signals: the bus surrender destination detection strobe signal and the bus surrender destination determination strobe signal, it is possible to respond to multiple bus surrender requests while maintaining the conventional signal format, and it is managed by the master. It is now possible to rationally control a bus system in which a master and multiple slaves share a single data bus.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a bus system for explaining the bus control method according to the present invention, and FIG. 2 is a time chart when there are bus surrender requests from two slaves. Figure 3 is a diagram for explaining the conventional technology. l4...
- Bus surrender request signal line, 15... Bus surrender destination detection strobe signal line, l6... Bus surrender destination determination strobe signal line, M... Master, S1 to So
...Slave, DB...Data bus, BRQ...
Bus surrender request signal, BPR... bus surrender destination detection strobe signal, BPW... bus surrender destination determination strobe signal, HOLD... signal requesting bus surrender, H
LDA: Bus surrender permission signal.

Claims (1)

[Claims] In a bus system configured such that one data bus managed by a master is shared by the master and a plurality of slaves, a bus surrender request signal line to which a bus surrender request signal from the slave is output; A bus surrender destination detection strobe signal line that is put into a strobe state based on the output of a surrender request signal to the bus surrender request signal line, and a bus surrender destination detection strobe signal line that outputs a bus surrender destination determination strobe signal from the master. A predetermined strobe signal line is provided, and a unique slave ID code is assigned to each slave,
When the slave outputs a bus handover request signal, the master transfers the bus based on the bus handover request signal from the slave having the slave ID code that matches the bus handover destination determination strobe signal output from the master. A bus control system characterized in that the slave is configured to give a bus surrender permission signal to the slave.