JPS587097B2 - digital circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital circuit having a function of preventing malfunctions caused by external noise during digital signal transmission.

Generally, when digital signals are transmitted over a relatively long distance, they are often affected by external noise generated in the wiring and the like between them.

As a noise malfunction prevention function in conventional digital circuits, there is a delay circuit provided on the output side of the signal generating circuit or within the receiving circuit.

FIG. 1 shows a block diagram of such a conventional data circuit, in which 1 is a data transmitting circuit, 23 to 2 are delay circuits, 3 is a data receiving circuit, and 4a to 4n are data signals. Data signals 4a to 4n of circuit 1 are input to data receiving circuit 3 after noise is absorbed by delay circuits 2a to 2n, respectively.

However, there are various problems in providing such a conventional malfunction prevention circuit as a general-purpose circuit due to the combination of the delay time of the delay circuit and the operating speed of the device.

The present invention has been made in view of these points, and it is an object of the present invention to provide a digital circuit that prevents noise malfunctions without using a delay circuit.

An embodiment of the present invention shown in FIG. 2 will be described below.

In Fig. 2, 1 is a data transmitting circuit, 2 is a signal receiving circuit, 3a to 3n are inverter circuits, 4a1 to 4an are data, 4b1 to 4bn are inverted data, 53 to 5n are seven exclusive OR circuits, and 6 is a NAND circuit. , 7a~In
8 is a data validity determination signal, and 8 is a retransmission request signal.

Next, the operation will be explained using FIG.

First, the general operation is to transmit data 4a from data transmitting circuit 1.
1 and inverted data 4b inverted by the inverter circuit 3a.
At t, an exclusive OR circuit 5a on the data receiving side checks whether data 4at+4bt is received as inverted, and if it is inverted, a data validity determination signal 7a is output.

This data judgment signal is sent to 7a to 7n by the NAND circuit 6.
If any one of them is not output, a retransmission request signal 8 is output to the data transmission circuit 1.

Next, as an individual example, we will first explain the operation when no noise is present on all data lines.

At this time, data 4a1 to 4an and inverted data 4b1 to 4
Exclusive OR circuit 5 with bn inverted
Since data validity determination signals 7a-In are output for all data lines since the signals are received by ax-5an, the re-selection request signal 8 is not output as shown in FIG. 3A.

Therefore, the data 4a1 to 4an are input to the data receiving circuit 2 as valid.

Next, if noise is coming to at least one of the data lines (for example, the data line 4a1), as shown in FIG. Therefore, the exclusive OR circuit 5a generates a data validity determination signal?
Even if a is not output and γb to γn are output, the NAND circuit 6 determines that the data of the retransmission request signal 8 input to the output data receiving circuit 2 is invalid.

As described above, according to the present invention, instead of using a delay circuit to prevent noise malfunctions, data received at the same time and inverted data are directly compared to determine the validity of the data, and it is determined that the data is invalid. In this case, since a retransmission request signal is output to control the operation of the transmitting circuit to prevent malfunction, it is possible to receive data from devices of any operating speed, and has the advantage of being versatile.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional digital circuit, Figure 2 is a block diagram showing a conventional digital circuit.
The figure is a block diagram showing one embodiment of the present invention, and FIG. 3 is a signal waveform diagram showing signals at various parts in FIG. 2. In the figure, 1 is a data transmission circuit, 3a to 3n are inverter circuits, 5a to 5n are exclusive OR circuits, and 6
is a NAND circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A transmitting circuit for transmitting a data signal, an inverting circuit disposed on the transmitting side together with the transmitting circuit and transmitting an inverted signal obtained by inverting the data signal at the same time as the data signal, and a transmitting circuit for transmitting the data signal. A data signal determination circuit is provided on the receiving side and compares the received data signal and the inverted signal as they are to determine the validity of the data signal, and outputs a retransmission request signal if the data signal is invalid; A digital circuit characterized in that the operation of the transmitting circuit is controlled by an output signal of the circuit. 2. The data signal determination circuit includes a plurality of exclusive OR circuits inputting the received data signal and the inverted signal;
2. The digital circuit according to claim 1, further comprising a NAND circuit whose input is the output of the exclusive OR circuit.