JPS62174864A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To confirm a trap factor, a processor condition, a program travelling condition, etc., by providing a circuit to connect the division between processors with one signal line and a circuit to inform a trap detecting signal by interrupting not only to one's own processor but to other processor by the circuit. CONSTITUTION:To a bus 1, a processor 2 and a memory 3 are connected and a trap factor detecting circuit 4 is connected. A processor-division signal transmitting receiving circuit 5 is connected to a traps factor detecting circuit 4 and a two way bus 6 and a CPU 2. For a tristate gate circuit 51 of the transmitting receiving circuit 5, when a signal 55 of a pulse generator 53 is a logical level '1', a gate is opened, the output of a logical level '0' is also '1' by the logical level '0' of a traps factor signal 54 and '1' is sent to a two way direction bus 6. On the other hand, the signal 55 of the pulse generator 53 is the logical level '0', the signal of a gate circuit 51 comes to be a high impedance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] The present invention relates to a multiprocessor system that synchronizes by notifying IJ41L, particularly other processors, of the detection timing of a trap factor.

[Prior Art j Conventionally, the trap factor detection circuit in a multiprocessor system is unique to each processor, and if a trap factor is detected in any processor, a signal may be sent to the outside. Signal from outside? There was no idea that other processors could synchronize all of this and start arbitrary programs.

[Problem to be solved by the invention J] In the conventional multiprocessor system described above, there was no signal transmission/reception with the outside when a trap cause sound was detected. The problem was that the other processors were operating regardless of this, and it was unclear which processors the other processors were in at any given time.

[Means for solving the fish industry problem J The multiprocessor system of the present invention includes a circuit for connecting the processors with one signal line, and an engineered circuit for the circuit.
Trap detection signal? It has a circuit that notifies not only its own processor but also other processors by interrupt.

[Example J Next, the present invention will be explained with reference to all the drawings.

An embodiment of the present invention shown in FIG. 1? Referring to the entire block diagram shown, a processor 2 and a memory 3 are connected to a bus 1. A trap factor detection circuit 4 is also connected to the bus 1 . The inter-processor signal transmission/reception circuit 5 includes a trap factor detection circuit 4. A bidirectional bus 6 is connected to the CPU 2. The tristate gate circuit 51 of the transmitter/receiver circuit 5 is opened when the signal 55 of the pulse generator 53 is at the logic level "1", and the gate is opened when the logic level of the trap factor signal 54 is "0°".
The output of logic level 10'' is also sent to the bidirectional bus 6 at logic level 61. On the other hand, when the signal 55 from the pulse generator 53 has a logic level of 10°, the gate circuit 51
The signal becomes high impedance. Normally, the logic level of the signal from the pulse generator 53 is 0'', so if the trap factor signal 54 is 5 μs, the pulse generator 53 sends a pulse signal with a slightly delayed timing (Figure 2). In addition, the trap factor signal 54 and the signal 55 from the pulse generator 53 are input to the gate circuit 51 at the timing shown in FIG.

When the logic level of the signal 55 is 10'', the gate circuit 51
The signal is high impedance, 1,'1: signal 55
When the logic level of the signal 55 becomes 1", the signal of the gate circuit 51 is high impedance, and when the logic level of the signal 55 becomes 1", the gate of the gate circuit 51 is opened, and the trap factor at this time is Since the logic level of the signal 54 is '1', the signal of the gate circuit 51 is sent to the bidirectional bus at the convenient timing shown in FIG.
Since the logic level of is normally “0”, the gate circuit 52
is normally open. Therefore, signals sent from other processors via the bidirectional bus 6 are sent to the CPU 2 through the gate circuit 52. The CPU 2 executes all necessary processing based on this signal.

[Effect of the Invention J As explained above, the present invention can transmit and receive signals with an external processor not only due to trap factors generated in the own processor but also due to trap factors generated in other processors.
Can you check trap factors, processor status, program running status, etc. on all processors with offline monitors? There are effects that can be confirmed.

[Brief explanation of drawings]

Figure 1 is a block diagram of MQ tlJ, which is a part of the present invention.
The figure is a timing chart when a trap factor r occurs in the CPU of FIG. 1. 1: Bus, 2: UPU, 3: Memory, 4 Nidrap factor detection circuit, 5: Inter-processor signal reception circuit, 6: Bidirectional bus, 51, 52 Nitristate gate circuit, 53
: Pulse generator, 54 Nidrap factor signal, 55
: Trap factor signal passed through the pulse generator, 56
:signal. 7, T″X,

Claims (1)

[Claims] In a multiprocessor system where multiple processors are connected by one communication bus and operate by interfering with each other, when a trap factor is detected in any processor as a peripheral circuit of each processor, the trap factor detection signal is automatically transmitted. A multiprocessor system having means for notifying a processor as an interrupt and means for similarly notifying a trap factor detection signal to other processors, and all processors in the system enter offline processing at the same time. .