JPH0669978A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To make communication without notifying an Endian of an opposite processor by unifying the Endian of communication between processors. CONSTITUTION:When a packet from a little Endian processor 3 or 8 is received by a big Endian processor 13 or 19, an Endian conversion processing section 15 or 21 of the big Endian processor 13 or 19 converts the little Endian of the received packet data into the big Endian. When the big Endian processor 13 or 19 sends a packet to the little Endian processor 3 or 8, the big Endian processor 13 or 19 uses the Endian conversion processing section 15 or 21 to convert the packet data generated as the bit endian by a packet processing section 16 or 22 into the data with the little Endian and sends the data to the opposite processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to packet communication in which one or more little endian processors and one or more big endian processors are mixed in a device and are tightly coupled by a bus. The present invention relates to an interprocessor communication system of a device.

[0002]

2. Description of the Related Art Conventionally, the endian of a processor which is tightly coupled by a bus in a processor of this type is unified into either little endian or big endian. Therefore, endian conversion processing is performed in interprocessor communication. Not at all.

[0003]

In the above-mentioned interprocessor communication system of the conventional multiprocessor system, since the endian of the processors is unified, there is no endian conversion function, and processors of different endian are included in the packet communication device. When tightly coupled, there was a problem that communication between processors was not possible.

An object of the present invention is a multiprocessor system in which a little endian processor and a big endian processor are mixed, and these are tightly coupled by a bus. The big endian processor performs an endian conversion process and performs interprocessor communication. An endian is unified as a little endian, and it is to provide an inter-processor communication method capable of performing inter-processor communication without being aware of the endian of the partner processor.

[0005]

An interprocessor communication system according to the present invention is a multiprocessor system that includes one or more little endian processors and one or more big endian processors and is tightly coupled by a bus. The big endian processor is provided with endian conversion means for performing endian conversion processing, when transmitting data on the bus, the endian conversion means converts the data to little endian, and when data is received from the bus,
The endian converting means converts the received data from little endian to big endian.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a packet communication device which is a multiprocessor system for explaining an embodiment of the present invention. In FIG. 1, as an example of a multiprocessor system in which one or more little endian processors and one or more big endian processors are mixed and tightly coupled by a bus 2, a packet communication device 1
Is composed of little endian processors 3 and 8 and big endian processors 13 and 19, and the little endian processors 3 and 8 are bus control units 4 and 9, packet processing units 5 and 10, and line control unit 6, respectively. And the big endian processors 13 and 19, respectively, and the bus controllers 14 and 2 respectively.
0, endian conversion processing units 15 and 21, packet processing units 16 and 22, and line control units 17 and 23.

First, the little endian processor 3
Or, the case where inter-processor communication is performed between the big endian processor 13 or 19 will be described.

In this case, the line control unit 6 or 11 of the little endian processor 3 or 8 receives the data from the line 7 or 12, and the packet processing unit 5 or 1
0 creates a little endian data packet,
The bus control unit 4 or 9 transmits this packet to the bus 2 as little endian.

On the other hand, the big endian processor 13
Alternatively, the bus controller 14 or 20 receives the packet from the little endian processor 3 or 8. Then, the endian conversion processing unit 15 or 21 converts the received packet from little endian to big endian. At this time, the endian conversion processing unit 15 or 21 converts the packet data from big endian to little endian regardless of the endian of the transmission source processor. The endian-converted packet is processed by the packet processing unit 16 or 22 and then sent to the line 8 or 24 by the line control unit 17 or 23.

In other words, in this case, the big endian processor 13 or 19 which is the receiving processor performs endian conversion in the packet receiving process, thereby realizing inter-processor communication as little endian.

The big endian processor 13
Alternatively, when a packet is transmitted from 19 to the little endian processor 3 or 8, the packet is as follows.

The line controller 17 or 23 of the big endian processor 13 or 19 is connected to the line 18 or 2
Data from the packet processing unit 16 or 2
At 2, a packet of big endian data is generated. The endian conversion processing unit 15 or 21 converts the big endian data of the packet generated by the packet processing unit 16 or 22 into little endian.
At this time, the endian conversion unit 15 or 21 converts the packet data from big endian to little endian regardless of the endian of the destination processor. The bus control unit 14 or 20 transmits the packet converted into the little endian by the endian conversion processing unit 15 or 21 onto the bus 2.

On the other hand, the little endian processor 3 or 8 is the big endian processor 13 or 19
The little endian packet is received from the bus control unit 4 or 9 and processed by the packet processing unit 5 or 10, and then the line control unit 6 or 11 causes the line 7 or 12 to be processed.
Send to.

In other words, in this case, the big endian processor 13 or 19 which is the transmission side processor performs the endian conversion processing in the packet transmission processing, thereby realizing inter-processor communication as little endian.

Next, a case where inter-processor communication is performed between the big endian processor 13 and the big endian processor 19 will be described.

Assuming a transmission / reception process in the case of transmitting a packet from the big endian processor 13 to the big endian processor 19, it is as follows. The line control unit 17 of the big endian processor 13 receives the data from the line 18, and the packet processing unit 16 generates a big endian packet. The endian processing unit 15 converts the big endian packet generated by the packet processing unit 16 into little endian. At this time, the endian conversion processing unit 15 converts the packet from big endian to little endian regardless of the endian of the destination processor. The bus control unit 14 transmits the packet converted into the little endian by the endian conversion processing unit 15 onto the bus 2.

On the other hand, the big endian processor 19
Receives the little endian packet from the big endian processor 13 at the bus control unit 20. The endian conversion processing unit 21 converts the received packet from little endian to big endian.
At this time, the endian conversion processing unit 21 converts the endian conversion processing from big endian to little endian regardless of the endian of the destination processor. The endian converted packet is processed by the packet processing unit 22 and then sent to the line 24 by the line control unit 23.

In other words, in this case, inter-processor communication is performed by the big endian processor 13, which is the transmitting processor, performing packet transmission processing, and the big endian processor 19, which is the receiving processor, performing packet end processing during packet reception processing. Is realized as little endian.

Next, the little endian processor 3
Then, a case where inter-processor communication is performed between the little endian processors 8 will be described.

The transmission process for transmitting a packet from the little endian processor 3 to the little endian processor 8 is as follows.

In this case, the transmission processing is similar to the processing of the little endian processor 3 or 8 when the packet is transmitted from the little endian processor 3 or 8 to the big endian processor 15 or 19. Further, the receiving process is the same as the process of the little endian processor 3 or 8 when the packet is transmitted from the big endian processor 13 or 19 to the little endian processor 3 or 8.

[0023]

As described above, according to the present invention, by the endian conversion processing function provided in the big endian processor, communication between tightly coupled processors having different endians is unified as a little endian. This has an effect that communication can be performed without being aware of the endian of the communication partner processor.

[0024]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a packet communication device in which endians are mixed to explain an embodiment of the present invention.

[Explanation of symbols]

 1 packet communication device 2 bus 3,8 little endian processor 4,9,14,20 bus control unit 5,10,16,22 packet processing unit 6,11,17,23 line control unit 7,12,18,24 terminal Accommodating line group 13,19 Big endian processor 15,21 Endian conversion processing unit

Claims (1)

[Claims] 1. In a multiprocessor system, which comprises one or more little endian processors and one or more big endian processors and is tightly coupled by a bus, an endian conversion is performed for the big endian processor. Means is provided, and when the data is transmitted onto the bus, the endian conversion means converts the data into little endian, and when the data is received from the bus,
An interprocessor communication system characterized in that the received data is converted from little endian into big endian by the endian conversion means.