JPS5874048A - 半導体集積回路の実装方式 - Google Patents

半導体集積回路の実装方式

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Publication number
JPS5874048A
JPS5874048A JP56173451A JP17345181A JPS5874048A JP S5874048 A JPS5874048 A JP S5874048A JP 56173451 A JP56173451 A JP 56173451A JP 17345181 A JP17345181 A JP 17345181A JP S5874048 A JPS5874048 A JP S5874048A
Authority
JP
Japan
Prior art keywords
chip
wiring board
pad
mounting
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56173451A
Other languages
English (en)
Inventor
Yukio Oda
小田　幸雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56173451A priority Critical patent/JPS5874048A/ja
Publication of JPS5874048A publication Critical patent/JPS5874048A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は、半導体集積回路の実装方式に関する。
従来この種の実装方式は、チップをパッケージに実装す
る従来の方法を示した藁１図と、その断面を示す第２図
のよう虻なっている。図において、１はチップ、２はこ
のチップ１を塔載するパッケージ′％３はチップ１とパ
ッケージ２を電気的に接続する９イヤ、４はワイヤ３を
取り付けるためにチップ管に形成されたパッド、５は同
じくワイヤ３を取□り付妙るためにパッケージ２−に形
成されたパッド、６はパッド５にパターンで電気的Ｋｍ
続されている端子である。
とのような構成において、上記パッケージ２には、デュ
アル・イン・ライン型や、チップキャリア型や、フラッ
トパッケージなど各種の型が使われている。
すなわち、電子装置を構成するためには、上記に述べた
種々のパッケージに実装された複数個の集積回路を総会
わせる必要がある。この目的から、従来は、配線板が用
いられる。第３図は、上記パッケージ２を実装した配線
板７を示したもので、７は上述のパッケージ２を端子６
を利用して取シ付け、内部で電気的接続を行なった配線
板である。
以上の実装方式では、パッケージ２の大きさによ〕、爽
装密度が制限さｈ１集積回路間の接続信号線路が長くな
る。従ってパッケージ２の端子６等の容量が線路に加わ
る等の問題から、信号の伝播時間が大きく表る欠点があ
った。
そこで、これらの欠点を改良するために第４図ないし第
５図に示すように１従来のフリップ・チップ実装方式が
実施されている。
図において、ｌは電気的接続を行危うためにノ・ンダを
生球状Ｋｌ＆〕上げた端子（以下バンプという）を形成
したチップ、８は上記バンプと溶融接着するための端子
（以下フリップ拳チップ・パッドという）を形成した配
線板である。９はチップｌのバンプと配線板８の７リツ
プ・チップ・パッド間の溶融接続されたハンダを示す。
このフリップ・チップ実装方式では、パッケージ２を配
線板７に実装する場合と比較して実装効率が上るが、チ
ップ１の占める面積からの制約があシ、実装密度の限界
が生じる。
従って、従来の電子装置は、以上のように集積回路自身
装するととＫよ〕構成されていたので、集積回路自身の
集積度が高くなっても、チップ間の距離が大きいと、装
置の寸法が大きくなシ、しいては信号の伝播遅煙時間が
大きくなり、処理速度が向上しない擾どの欠点があった
。
この発明は上述した従来例の欠点を除去するためＫなさ
れたもので、２個のチップを組み合わせて、配線板に実
装するととｋよシ、実装密度を２倍にすることを目的と
した半導体集積回路の実装方式を提供するものである。
以下、この発明の一実施例を第６図ないし第９図にもと
づいて説明する。図中、従来例と対応する箇所及び部品
には同一符号を付して説明する・第６図はこの発明の一
実施例を示す断面図であ夛、１ａは外部との信号接続お
よび給電をするためのワイヤ３を取シ付けるパッド４を
形成したチップ、ｌｂはフリップ・チップ実装をするえ
めに信号接続、給電及びチップ固定用のバンプ１０を形
成したチップであり、チップ１ａとチップ１ｂはパッド
及びバンプ形成面と反対側の面で接着される。
第７図は第６図の変形例を示す断面図であり、１１はチ
ップ１ａとｌｂを接着するときに、その間に介在させる
金属等の物質（以下介在物質という］である。
また、第８図は、上記の接着したチップの配線板８への
実装方式を示す図であり、１１ｇ９図は第８図の断面図
である。図において、１２ｔｊ：配線板８に形成された
ワイヤ接続用パッド、１３はチップｌｂを接続固定する
ために配線板８に形成されたフリップ・チップ・パッド
である。
こζで、チップ１ａと配線板８との電気的接続はパッド
４及びパッド１２を結ぶワイヤ３によ〕行カわれる。ま
た、チップｌｂと配線板８との電気的接続は、バンプｌ
Ｏと７リツプ・チップ・ノくラド１３とのハンダ接続に
よシ行なわれ、９はその溶融したハンダを示す。
上述し九ような実装方式によれば、第８図、第９図にお
いて、チップｌａ、ｌｂを第７図に示す構造のものとし
良場合、金属等の介在物質１１が放熱板の役割を果すと
ともに、チップの強度を上ぜるので、試験、組み立て等
の取扱いに有利である。
チップＩＩＬ、ｌｂを組み合わせる場合に、論理分割上
、関係の深い回路を組み合わせれば、集積回路間の線路
を短かくシ、信号遅延を小さくすることができる。
また、記憶素子をチップ１ａｓｌｂとして構成すれば、
１憶容量を容易に拡張することができるものであり、冗
長１路部分を組み合わせて、構成すれば、実装密度を犠
牲にすること々〈冗長設計が行なえる。
なお、−第８図において、配線板８の材質は従来のセラ
ミックに限らずその他の材料を用いても曳く、また、形
状も実施例は板で示したが他のどのような形状であって
もよく、上記実施例と同様の効果を奏する。
以上詳細に説明したように、この発明によれば二個のチ
ップを接着し、一方の面を７リツプ・チップ方式で、他
面をワイヤ・ボンディング方式によシ配線板に実装する
ことＫより、実装密度を高め、装置の小型化を計９．か
つ装置の性能を同上させる等の効果を奏する。
【図面の簡単な説明】
１！１＠１０チツプをパッケージに実装する従来の方式
を示した斜視図％纂２図α幕１図の断面図。 纂３＠ｌにパッケージを実装した配！ｌｉ板を示す斜視
（２）、纂４図に従来のフリツ１・チン１実装方式な示
す斜視図、ａ１５＠ｌα纂４図の断面図、纂６図。 纂７１ｍ＋１Ｈこの発明の一実施例を示す要部の断面図
。 ＩＮ８＠Ｉにこの発明の接着したチックを配ａｉｌ板＃
ｃ４！り付けた一実施例を示す斜視Ｓ、纂９図ｕ幕８図
の断面図である。 １・・・チップ、ｌａ−・バット管形成したチップ。 １ｂ・・・バングを形成したチップ、２・・・パッケー
ジ。 ３・・・ｉ［ｌ１ｌｉ！ワイヤ、４・−チックに形成さ
れたパッド。 ５・・・パッケージに形ｔｉＸされたパッド、６・・・
端子、７・・・配線板、８・・・フリツ、゛；“・チッ
プ用の配線板。 ：１　　・ ９・・・ハンダ、五〇・・・パン１． １１−・・ニーのチツ１のｆｌＩｌｉｒＭ間の介在物質
。 １２・・・配線＠＃Ｃ形５Ｘされたパッド。 １３・・・配線板に形成されたフリップ・チツ１・）Ｚ
・ｙＶ。 ％許出鵬人　三菱電機株式会社 代理人葛野信−（外１名） １．１ “′）′ １：、。 第１図 第２図

Claims (1)

    【特許請求の範囲】
  1. 半導体集積回路を、実装する方式において、二個の集積
    回路チップ（以下チップという）のうちの一つは信号接
    続および給電をワイヤで行なうためのパッドを形成し、
    他の一つは信号接続、給電およびチップ管固定するため
    のバンプを形成し、パッドま九はバンプと反対−の面で
    この二個の集積回路を直接に、あるいは介在物質を介し
    て間接に接着し、バンプ形成面は配線板にフリップ−チ
    ップ方式で実装し、パッド形成面は配線板との間をワイ
    ヤ・ボンディング方式で接続した仁とｔ−Ｗ徴とする半
    導体集積回路の実装方式。
JP56173451A 1981-10-29 1981-10-29 半導体集積回路の実装方式 Pending JPS5874048A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56173451A JPS5874048A (ja) 1981-10-29 1981-10-29 半導体集積回路の実装方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56173451A JPS5874048A (ja) 1981-10-29 1981-10-29 半導体集積回路の実装方式

Publications (1)

Publication Number Publication Date
JPS5874048A true JPS5874048A (ja) 1983-05-04

Family

ID=15960705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56173451A Pending JPS5874048A (ja) 1981-10-29 1981-10-29 半導体集積回路の実装方式

Country Status (1)

Country Link
JP (1) JPS5874048A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107445U (ja) * 1985-12-25 1987-07-09
JPH02170443A (ja) * 1988-12-22 1990-07-02 Fuji Electric Co Ltd 半導体集積回路装置の実装方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107445U (ja) * 1985-12-25 1987-07-09
JPH02170443A (ja) * 1988-12-22 1990-07-02 Fuji Electric Co Ltd 半導体集積回路装置の実装方式

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