JP2002134685A - 集積回路装置 - Google Patents
集積回路装置Info
- Publication number
- JP2002134685A JP2002134685A JP2000326776A JP2000326776A JP2002134685A JP 2002134685 A JP2002134685 A JP 2002134685A JP 2000326776 A JP2000326776 A JP 2000326776A JP 2000326776 A JP2000326776 A JP 2000326776A JP 2002134685 A JP2002134685 A JP 2002134685A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- conductive material
- integrated circuit
- circuit device
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
ップ・オン・チップ構造の集積回路装置を提供する。 【解決手段】 チップ・オン・チップ構造のICチップ
1及び2のうちのフレーム5に直接的には実装されてい
ないICチップ2の上面に導電材7を設け、この導電材
7をグランド電位となるフレーム5にワイヤ8で接続す
る。
Description
どして接合されることにより互いに電気的に接続された
複数のICチップを有する集積回路装置に関するもので
ある。
るにあたって、両方のチップをバンプを介して接合する
などして電気的に接続した構造(以下、「チップ・オン
・チップ構造」と称する)にする場合がある。このチッ
プ・オン・チップ構造を採用することによって、各チッ
プを別々に実装する場合に比して、実装面積を小さくで
きるというメリットがある。
は、図7に示すように、チップ・オン・チップ構造のI
Cチップ1及び2をフレーム5に単に積み重ねた構成に
なっていたので、特に高周波信号を取り扱う場合には、
外部ノイズをひろったり、内部チップからのノイズが回
り込んで、誤動作が発生したり、動作しないことがあっ
た。
る誤動作を低減したチップ・オン・チップ構造の集積回
路装置を提供することを目的とする。
め、第1のICチップと第2のICチップとが接合され
ることにより互いに電気的に接続された上で基板に実装
されて成る集積回路装置において、前記第1のICチッ
プと前記第2のICチップのうちの前記基板に直接的に
は実装されていない方のICチップの上面、または、前
記第1のICチップと前記第2のICチップとの間に導
電材を設けるとともに、該導電材を定電位点に接続して
いる。この構成により、シールド効果が高まり、外部ノ
イズの混入や内部チップで発生するノイズの回り込みが
抑制される。
を参照しながら説明する。図1は本発明の実施形態であ
る集積回路装置の断面図である。第1のICチップ1
と、第2のICチップ2とが、金などのバンプ3を介し
て電気的に接続されることにより、チップ・オン・チッ
プ構造となっている。第1のICチップ1と第2のIC
チップ2とはこれらのICチップが対向する方向にのみ
導電性を示す異方性導電フィルム4を挟んで熱圧着され
ることにより接合されている。その後、樹脂によりモー
ルドしてパッケージを形成したり、樹脂をポッティング
したりするが、一般的な方法なので説明は省略する。
ップ2が接合されていない側の面)をフレーム5側にし
てフレーム5に実装されている。第1のICチップ1と
フレーム5とはワイヤ6により電気的に接続されてい
る。フレーム5はグランドに接続される。フレーム5と
しては、樹脂封止ICを構成する金属からなるアイラン
ドや樹脂基板の表面に金属配線が形成された基板を用い
ることができる。
第2のICチップ2の上面(第1のICチップ1が接合
されていない側の面)には導電材7が設けられている。
導電材7は蒸着あるいははり付けにより形成することが
できる。導電材7の材質は、例えば銅やアルミや金であ
る。導電材7はワイヤ8によりグランド電位となるフレ
ーム5に接続されている。尚、図2に示すように、導電
材7をワイヤ9で第1のICチップ1に接続することに
より、第1のICチップ1を介して導電材7をフレーム
5に接続するようにしてもよい。尚、図2では、第1の
ICチップ1と第2のICチップ2とをバンプ3で直接
つなげた構造となっている。
導電材7に接触し、他端がフレーム5に導電性の材料で
接着または溶着されているとともに、矢印Aで示す方向
に力が働く金属性のバネ10により導電材7をフレーム
5に接続するようにしてもよい。また、図4に断面図を
示すように、チップ・オン・チップ構造のICチップ1
及び2の全体を導電材11で囲い込むとともに、導電材
11をフレーム5と導通状態にし、さらに、自然長より
も短くなった状態(すなわち、伸びようとする状態)に
ある導電性のバネ12により導電材7と導電材11とを
接続することによって、バネ12及び導電材11を介し
て導電材7をフレーム5に接続するようにしてもよい。
これらの各構成によれば、接着及び溶着技術が簡素化さ
れる。また、図3、4の場合、導電材7を設けないで、
第2のICチップ2の裏面と直接接触するようにしても
よい。
路装置の断面図、上面図を図5の(a)、(b)にそれ
ぞれ示す。尚、今までに説明した実施形態と同一部分に
は同一符号を付して説明を省略する。異方性導電フィル
ム4内に、すなわち、チップ・オン・チップ構造の2つ
のICチップ1と2との間には、バンプ3と接触しない
ように、金属性の導電材13が挟み込まれたり、差し込
まれたりしている。導電材13には異方性導電フィルム
4からはみ出している部分があり、この部分からワイヤ
14によりグランド電位となるフレーム5に接続されて
いる。尚、第1のICチップ1を介して導電材13をフ
レーム5に接続するようにしてもよいし、図3のような
バネ材を使用して接続するようにしてもよい。また、第
1のICチップ1の表面には複数のパッドが形成されて
いるが、判りやすくするためにワイヤ接続は省略してい
る。
ップ構造のICチップに導電材を別途組み込むととも
に、この導電材をグランドに接続しており、これによ
り、シールド効果を得ることができるので、外部ノイズ
の混入や内部チップで発生するノイズの回り込みが抑制
され、ノイズに起因して生じる誤動作が低減する。
をグランドに接続する構成となっているが、その他の定
電位点(例えば電源ラインなど)に接続するようにして
もよい。また、図6に示すように、図1の構成と図5の
構成とを組み合わせた構成、すなわち、導電材7と13
との両方を設けた構成であってもよい。
装置によれば、チップ・オン・チップ構造のICチップ
に導電材を組み込むとともに、その導電材を定電位点に
接続することによりシールド効果を得ているので、外部
ノイズの混入や内部チップで発生するノイズの回り込み
が抑制され、ノイズに起因して生じる誤動作が低減す
る。
図である。
断面図である。
装置の断面図である。
装置の断面図である。
装置の断面図及び上面図である。
装置の断面図及び上面図である。
装置の断面図である。
Claims (1)
- 【請求項1】 第1のICチップと第2のICチップと
が接合されることにより互いに電気的に接続された上で
基板に実装されて成る集積回路装置において、前記第1
のICチップと前記第2のICチップのうちの前記基板
に直接的には実装されていない方のICチップの上面、
または、前記第1のICチップと前記第2のICチップ
との間に設けられた導電材を定電位点に接続したことを
特徴とする集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000326776A JP2002134685A (ja) | 2000-10-26 | 2000-10-26 | 集積回路装置 |
US09/983,396 US20020050635A1 (en) | 2000-10-26 | 2001-10-24 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000326776A JP2002134685A (ja) | 2000-10-26 | 2000-10-26 | 集積回路装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002134685A true JP2002134685A (ja) | 2002-05-10 |
Family
ID=18803909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000326776A Pending JP2002134685A (ja) | 2000-10-26 | 2000-10-26 | 集積回路装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20020050635A1 (ja) |
JP (1) | JP2002134685A (ja) |
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WO2007080922A1 (ja) * | 2006-01-16 | 2007-07-19 | Nissan Motor Co., Ltd. | 半導体電力変換装置 |
JP2007251226A (ja) * | 2007-07-09 | 2007-09-27 | Nec Electronics Corp | 半導体装置 |
US7667312B2 (en) | 2002-09-18 | 2010-02-23 | Nec Electronics Corporation | Semiconductor device including a heat-transmitting and electromagnetic-noise-blocking substance and method of manufacturing the same |
JPWO2013153742A1 (ja) * | 2012-04-11 | 2015-12-17 | パナソニックIpマネジメント株式会社 | 半導体装置 |
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JP3581086B2 (ja) | 2000-09-07 | 2004-10-27 | 松下電器産業株式会社 | 半導体装置 |
US6818985B1 (en) * | 2001-12-22 | 2004-11-16 | Skyworks Solutions, Inc. | Embedded antenna and semiconductor die on a substrate in a laminate package |
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US20040124538A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Multi-layer integrated semiconductor structure |
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TW200522293A (en) * | 2003-10-01 | 2005-07-01 | Koninkl Philips Electronics Nv | Electrical shielding in stacked dies by using conductive die attach adhesive |
JP2006186053A (ja) * | 2004-12-27 | 2006-07-13 | Shinko Electric Ind Co Ltd | 積層型半導体装置 |
US20060157866A1 (en) * | 2005-01-20 | 2006-07-20 | Le Thoai T | Signal redistribution using bridge layer for multichip module |
US7786572B2 (en) * | 2005-09-13 | 2010-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | System in package (SIP) structure |
KR100850072B1 (ko) * | 2006-11-03 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 웨이퍼 컷 앵글의 보상 기능을 가지는 이온주입장치 및이를 이용한 이온주입방법 |
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JP5454438B2 (ja) * | 2010-09-27 | 2014-03-26 | 株式会社デンソー | 半導体モジュール |
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- 2000-10-26 JP JP2000326776A patent/JP2002134685A/ja active Pending
-
2001
- 2001-10-24 US US09/983,396 patent/US20020050635A1/en not_active Abandoned
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JPH0513663A (ja) * | 1991-07-09 | 1993-01-22 | Fujitsu Ltd | 半導体装置と半導体チツプの実装方法 |
JPH06112401A (ja) * | 1992-09-25 | 1994-04-22 | Nippon Telegr & Teleph Corp <Ntt> | マルチチップ実装回路 |
JPH06163822A (ja) * | 1992-11-27 | 1994-06-10 | Sharp Corp | 集積回路チップおよび複合半導体装置 |
JP2000252409A (ja) * | 1999-02-26 | 2000-09-14 | Rohm Co Ltd | 半導体チップ |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7667312B2 (en) | 2002-09-18 | 2010-02-23 | Nec Electronics Corporation | Semiconductor device including a heat-transmitting and electromagnetic-noise-blocking substance and method of manufacturing the same |
WO2007080922A1 (ja) * | 2006-01-16 | 2007-07-19 | Nissan Motor Co., Ltd. | 半導体電力変換装置 |
JP2007251226A (ja) * | 2007-07-09 | 2007-09-27 | Nec Electronics Corp | 半導体装置 |
JP4657262B2 (ja) * | 2007-07-09 | 2011-03-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JPWO2013153742A1 (ja) * | 2012-04-11 | 2015-12-17 | パナソニックIpマネジメント株式会社 | 半導体装置 |
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