JPS5873141A - マルチチツプｌｓｉパツケ−ジ - Google Patents
マルチチツプｌｓｉパツケ−ジInfo
- Publication number
- JPS5873141A JPS5873141A JP17078281A JP17078281A JPS5873141A JP S5873141 A JPS5873141 A JP S5873141A JP 17078281 A JP17078281 A JP 17078281A JP 17078281 A JP17078281 A JP 17078281A JP S5873141 A JPS5873141 A JP S5873141A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat
- substrate
- heat sink
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000919 ceramic Substances 0.000 claims abstract description 9
- 230000005855 radiation Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 150000002739 metals Chemical group 0.000 claims 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 3
- 238000005245 sintering Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078281A JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプｌｓｉパツケ−ジ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17078281A JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプｌｓｉパツケ−ジ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873141A true JPS5873141A (ja) | 1983-05-02 |
| JPS624859B2 JPS624859B2 (enrdf_load_stackoverflow) | 1987-02-02 |
Family
ID=15911267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17078281A Granted JPS5873141A (ja) | 1981-10-27 | 1981-10-27 | マルチチツプｌｓｉパツケ−ジ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873141A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62116440U (enrdf_load_stackoverflow) * | 1986-01-14 | 1987-07-24 |
-
1981
- 1981-10-27 JP JP17078281A patent/JPS5873141A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62116440U (enrdf_load_stackoverflow) * | 1986-01-14 | 1987-07-24 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS624859B2 (enrdf_load_stackoverflow) | 1987-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW502406B (en) | Ultra-thin package having stacked die | |
| US6650006B2 (en) | Semiconductor package with stacked chips | |
| KR100269528B1 (ko) | 고성능 멀티 칩 모듈 패키지 | |
| CN207320090U (zh) | 电子器件和电子芯片 | |
| JP4493121B2 (ja) | 半導体素子および半導体チップのパッケージ方法 | |
| JPH0548000A (ja) | 半導体装置 | |
| JPH07221218A (ja) | 半導体装置 | |
| JP2005217405A (ja) | 熱放出形半導体パッケージ及びその製造方法 | |
| KR20200135503A (ko) | 모놀리식 마이크로파 통합 회로(mmic) 냉각 구조 | |
| CN114765142B (zh) | 电子封装件及其制法 | |
| TW200945545A (en) | Package-on-package semiconductor structure | |
| JPH06224334A (ja) | マルチチップモジュール | |
| CN113451244B (zh) | 双面散热的mosfet封装结构及其制造方法 | |
| US6034425A (en) | Flat multiple-chip module micro ball grid array packaging | |
| CN100550360C (zh) | 具有底部散热的设备和系统及其制造方法 | |
| JPH10335521A (ja) | 半導体装置 | |
| CN103050455A (zh) | 堆叠封装结构 | |
| KR20030045950A (ko) | 방열판을 구비한 멀티 칩 패키지 | |
| CN218957731U (zh) | 用于集成电路的封装 | |
| JPH09213847A (ja) | 半導体集積回路装置及びこの製造方法並びにそれを用いた電子装置 | |
| JPS5873141A (ja) | マルチチツプｌｓｉパツケ−ジ | |
| JP2003258165A (ja) | 半導体装置 | |
| JP4237116B2 (ja) | 半導体装置およびその製造方法 | |
| JPH08162575A (ja) | 半導体装置およびその製造方法 | |
| KR20010009153A (ko) | 박형 시스템 대응 고방열 히트스프레다 부착 패키지구조 및 그의 제조 방법 |