JPS5866420A - ２導体のデ−タカラムを有する記憶論理アレイ - Google Patents

２導体のデ−タカラムを有する記憶論理アレイ

Info

Publication number
JPS5866420A
JPS5866420A JP57135275A JP13527582A JPS5866420A JP S5866420 A JPS5866420 A JP S5866420A JP 57135275 A JP57135275 A JP 57135275A JP 13527582 A JP13527582 A JP 13527582A JP S5866420 A JPS5866420 A JP S5866420A
Authority
JP
Japan
Prior art keywords
conductor
data
output
column
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57135275A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0315382B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ウイリアム・ナツプ
ウイリアム・ダン
ケント・エフ・スミス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Instrument Corp filed Critical General Instrument Corp
Publication of JPS5866420A publication Critical patent/JPS5866420A/ja
Publication of JPH0315382B2 publication Critical patent/JPH0315382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP57135275A 1981-08-05 1982-08-04 ２導体のデ−タカラムを有する記憶論理アレイ Granted JPS5866420A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8123966 1981-08-05
GB8123966 1981-08-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2099482A Division JPH0369095A (ja) 1981-08-05 1990-04-17 ２導体のデータカラムを有する記憶論理アレイに使用する記憶セル

Publications (2)

Publication Number Publication Date
JPS5866420A true JPS5866420A (ja) 1983-04-20
JPH0315382B2 JPH0315382B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-02-28

Family

ID=10523722

Family Applications (2)

Application Number Title Priority Date Filing Date
JP57135275A Granted JPS5866420A (ja) 1981-08-05 1982-08-04 ２導体のデ−タカラムを有する記憶論理アレイ
JP2099482A Pending JPH0369095A (ja) 1981-08-05 1990-04-17 ２導体のデータカラムを有する記憶論理アレイに使用する記憶セル

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2099482A Pending JPH0369095A (ja) 1981-08-05 1990-04-17 ２導体のデータカラムを有する記憶論理アレイに使用する記憶セル

Country Status (2)

Country Link
US (2) US4414547A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (2) JPS5866420A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58179997A (ja) * 1982-01-13 1983-10-21 スペリ・コ−ポレ−シヨン メモリ論理アレイ回路
JPS61280120A (ja) * 1985-06-04 1986-12-10 ジリンクス・インコ−ポレイテツド コンフイグラブルロジツクアレイ
JPH0369095A (ja) * 1981-08-05 1991-03-25 General Instr Corp ２導体のデータカラムを有する記憶論理アレイに使用する記憶セル

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US4669063A (en) * 1982-12-30 1987-05-26 Thomson Components-Mostek Corp. Sense amplifier for a dynamic RAM
US4508977A (en) * 1983-01-11 1985-04-02 Burroughs Corporation Re-programmable PLA
US4546273A (en) * 1983-01-11 1985-10-08 Burroughs Corporation Dynamic re-programmable PLA
US4520465A (en) * 1983-05-05 1985-05-28 Motorola, Inc. Method and apparatus for selectively precharging column lines of a memory
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
CN1003549B (zh) * 1985-01-25 1989-03-08 株式会社日立制作所 半导体集成电路器件
JPH0793568B2 (ja) * 1985-07-16 1995-10-09 日本電気株式会社 フリップフロップ回路
US4700187A (en) * 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4845633A (en) * 1985-12-02 1989-07-04 Apple Computer Inc. System for programming graphically a programmable, asynchronous logic cell and array
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US5089973A (en) * 1986-11-07 1992-02-18 Apple Computer Inc. Programmable logic cell and array
US5019736A (en) * 1986-11-07 1991-05-28 Concurrent Logic, Inc. Programmable logic cell and array
SU1672535A1 (ru) * 1987-12-25 1991-08-23 Всесоюзный научно-исследовательский аккумуляторный институт Электрический аккумул тор
US4847612A (en) * 1988-01-13 1989-07-11 Plug Logic, Inc. Programmable logic device
USRE34444E (en) * 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
US5023606A (en) * 1988-01-13 1991-06-11 Plus Logic, Inc. Programmable logic device with ganged output pins
US4931946A (en) * 1988-03-10 1990-06-05 Cirrus Logic, Inc. Programmable tiles
US4972105A (en) * 1989-09-22 1990-11-20 The U.S. Government As Represented By The Director, National Security Agency Programmable configurable logic memory
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5144166A (en) * 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5648732A (en) * 1995-10-04 1997-07-15 Xilinx, Inc. Field programmable pipeline array
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
WO2002013000A2 (de) 2000-06-13 2002-02-14 Pact Informationstechnologie Gmbh Pipeline ct-protokolle und -kommunikation
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
AU2002347560A1 (en) 2001-06-20 2003-01-02 Pact Xpp Technologies Ag Data processing method
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
ATE402446T1 (de) 2002-02-18 2008-08-15 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6920510B2 (en) * 2002-06-05 2005-07-19 Lsi Logic Corporation Time sharing a single port memory among a plurality of ports
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
EP1676208A2 (en) 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
JP2009524134A (ja) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
US7693257B2 (en) * 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
US20100272811A1 (en) * 2008-07-23 2010-10-28 Alkermes,Inc. Complex of trospium and pharmaceutical compositions thereof

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GB1260777A (en) * 1969-08-18 1972-01-19 Marconi Co Ltd Improvements in or relating to memory cells
GB1260426A (en) * 1969-08-18 1972-01-19 Marconi Co Ltd Improvements in or relating to memory cells
GB1347470A (en) * 1970-12-22 1974-02-27 Marconi Co Ltd Memory cells
GB1457423A (en) * 1973-01-17 1976-12-01 Nat Res Dev Associative memories
FR2266259B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1974-03-26 1977-09-30 Thomson Csf
JPS515541A (ja) * 1974-07-03 1976-01-17 Hitachi Ltd Hosenshidogataseigyoban
US3969708A (en) * 1975-06-30 1976-07-13 International Business Machines Corporation Static four device memory cell
US4031522A (en) * 1975-07-10 1977-06-21 Burroughs Corporation Ultra high sensitivity sense amplifier for memories employing single transistor cells
US4068214A (en) * 1976-02-03 1978-01-10 Massachusetts Institute Of Technology Asynchronous logic array
JPS52111341A (en) * 1976-03-16 1977-09-19 Toshiba Corp Semiconductor memory device
US4069475A (en) * 1976-04-15 1978-01-17 National Semiconductor Corporation MOS Dynamic random access memory having an improved sense and restore circuit
US4081701A (en) * 1976-06-01 1978-03-28 Texas Instruments Incorporated High speed sense amplifier for MOS random access memory
US4207556A (en) * 1976-12-14 1980-06-10 Nippon Telegraph And Telephone Public Corporation Programmable logic array arrangement
US4293783A (en) * 1978-11-01 1981-10-06 Massachusetts Institute Of Technology Storage/logic array
JPS5668990A (en) * 1979-11-08 1981-06-09 Nec Corp Memory circuit
JPS563838U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1979-06-22 1981-01-14
US4342102A (en) * 1980-06-18 1982-07-27 Signetics Corporation Semiconductor memory array
JPS5736498A (en) * 1980-08-13 1982-02-27 Hitachi Ltd Multisplit longitudinal type rom
US4351034A (en) * 1980-10-10 1982-09-21 Inmos Corporation Folded bit line-shared sense amplifiers
US4414547A (en) * 1981-08-05 1983-11-08 General Instrument Corporation Storage logic array having two conductor data column

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0369095A (ja) * 1981-08-05 1991-03-25 General Instr Corp ２導体のデータカラムを有する記憶論理アレイに使用する記憶セル
JPS58179997A (ja) * 1982-01-13 1983-10-21 スペリ・コ−ポレ−シヨン メモリ論理アレイ回路
JPS61280120A (ja) * 1985-06-04 1986-12-10 ジリンクス・インコ−ポレイテツド コンフイグラブルロジツクアレイ

Also Published As

Publication number Publication date
JPH0369095A (ja) 1991-03-25
US4442508A (en) 1984-04-10
US4414547A (en) 1983-11-08
JPH0315382B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-02-28

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