JPS5863146A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the high integration of a semiconductor device and to improve the reliability at the contact of the device by rediffusing to a diffused layer in a C-MOS structure without necessity of masking, thereby forming a deep diffused layer only in the vicinity of a contact hole. CONSTITUTION:Since diffused layers 5, 10 are partly formed deeply by the rediffusion utilizing the OED effect in an oxidative atmosphere, both N-type and P-type diffused layers 5, 10 can be simultaneously deeply formed, with excellent workability as compared with a conventional rediffusing method by separately injecting impurities of different conductive types by twice maskings. Since the layers 5, 10 are laterally expanded by deeply forming the layers 5, 10 in the vicinity of a contacting hole 7, a danger that a wiring material 8 and a semiconductor substrate 1 shortcircuit can be avoided. As a result, since large margin can be provided against the displacement of the hole 7 to the layers 5, 10, an overlapped amount can be reduced, and high integration can be performed.

Description

[Detailed Description of the Invention] In general, highly integrated MOS type chihiro-type or bipolar type semiconductor devices often have a structure in which wiring made of aluminum or the like contacts a shallow diffusion layer formed on the surface of the semiconductor substrate. To make contact between the wiring material and the shallow diffusion, a contact hole is formed in a silicon oxide film interposed as an insulating film between them, and the wiring material is provided through the contact hole to establish electrical contact. There is.

However, when manufacturing a highly densely integrated semiconductor device such as 1tLsI using such contact, there are some problems.

■ An alloy of the wiring material and the semiconductor is formed at the contact between the wiring material and the diffusion layer, but if the diffusion layer is formed extremely shallow, the wiring material may penetrate through the diffusion layer and reach the semiconductor substrate. As a result, a bonded state cannot be obtained.

■ In high-millimeter LSIs, reactive ion etching (RIE) is often used to puncture the interconnection material. However, if aluminum is used as the wiring material, R
When etching with IE, the selectivity between aluminum and the silicon substrate is very low, so if the contact hole is large, the silicon substrate located below the contact hole will also be etched, and the aluminum will come into contact not only with the diffusion layer but also with the silicon substrate. Sometimes I end up doing it. For this reason, it is necessary to have a large overlap between the aluminum and the contact hole, and this is the reason why the LS
This is an obstacle to improving the integration density of I.

■ If there is little overlap between the contact hole and the diffusion layer, there is a risk of contact between the wiring material and the silicon substrate.
It is necessary to provide sufficient overlap, which, like the case (2) above, is an obstacle to improving the LSI integration density.

In order to solve the above-mentioned problems, a method has been developed in which the diffusion layer in the vicinity of the transistor channel is kept shallow while the diffusion layer is formed deep only in the vicinity of the contact hole.

The case of manufacturing a MOS LSI using this method will be explained with reference to FIG.

As shown in FIG. 1, a thick field oxide film 2 is formed on a semiconductor substrate I, for example, a P-type silicon substrate, by a well-known selective oxidation technique.

Next, as shown in Figure 1), after forming a gate oxide film 3 on the surface of the semiconductor substrate 1, polycrystalline silicon 4 is provided on this surface, and then phosphorus is diffused into the polycrystalline silicon 4. and use it as a gate electrode.

After this, he selectively etched away the polycrystalline silicon 4 and gate oxide film 3 using the 7-oto-clean technique, and then implanted impurity ions using the polycrystalline silicon 4 as a mask to form source and drain layers. Naruen@, M5. s
form. In this case, 40 arsenic atoms are added as impurities.
KeV.

Shallow diffusions M5,5 are formed by ion implantation with a depth of 2.times.101101l''.

Next, a thick oxide film 6 that will become an insulating film is applied to the entire surface using, for example, CV
D (Chemical Vapor Deposit
tion) technology.

Next, as shown in the same figure (C), after opening a contact hole 7.7 in the CVD oxide film 6, through this contact hole 7.7,
Example 1: When phosphorus is diffused into the diffusion layer 5.5 by exposing it to an atmosphere of 1000° C. and POCI for 15 minutes, the diffusion layer 5.5 is formed which is deep only in the vicinity of the contact hole 7.

Thereafter, a wiring material 8 such as aluminum is deposited on the entire surface, and then patterned by photolithography to bring it into contact with the diffusion layer 5.6 as shown in FIG. 2(2).

However, in the conventional method, diffusion through the contact hole 7)
In order to further diffuse phosphorus as an N-type impurity into #5 and form it only in the vicinity of the contact hole 7, CMO8 SEIZO, which has both an N-type diffusion layer and a P-type diffusion layer, has an N-type diffusion layer. However, it could not be applied to the production of CMO8 semiconductor devices because it would increase the contact resistance for P diffusion layers. In this case, it is necessary to cover the contact hole that contacts the diffusion layer of the different molds with photoresist on one side at a time, and to diffuse different impurities separately, which requires two mask alignments, resulting in poor workability. But nine.

The present invention eliminates the above-mentioned drawbacks, improves workability by allowing re-diffusion into the diffusion layer without requiring mask alignment even in CMO8 SEIZO, and enables high eaves and density integration, as well as reliability of contact parts. The present invention provides a method for manufacturing a semiconductor device with excellent performance.

That is, the method of the present invention includes the steps of providing an insulating film on the upper surface of a diffusion layer formed on the surface of a semiconductor substrate, forming a contact hole in this insulating film, and forming a diffusion layer by following the contact hole. A process of oxidizing, a process of removing oxides formed on the surface of the diffusion layer, and a process of providing wiring material on the entire surface and making electrical contact with the diffusion layer through contact holes. That is.

In the present invention, the present invention is not limited to the case where only one of the ViN type diffusion layer and the P type diffusion layer is formed, and a CMO8Th structure in which both are provided in a diagonal manner may be used.

In the present invention, methods for oxidizing the diffusion layer through contact holes include heat treatment in a dry oxygen atmosphere;
Any method may be used, such as providing polycrystalline silicon in the contact hole and subjecting it to low-temperature wet oxidation.

When the diffusion layer is oxidized through the contact hole in this way, the OE
D effect (Oxidation EnhancedDif
fusion), excessive vacancies (vacanc') are introduced into the silicon forming the diffusion layer, causing multiplication and diffusion, forming a deep diffusion layer only near the contact whose surface has been oxidized, and other The portion remains as a shallow diffusion layer.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment in which a CMO8 semiconductor device is manufactured by the method of the present invention.

First, as shown in FIG. 2, an N-type silicon substrate is used as the semiconductor substrate 1, and after forming a P well 9 on a part of its surface by photolithography technology, an element forming area of the semiconductor substrate 1 is formed. A thick field oxide film 2 is formed by selective oxidation, leaving a portion where .

Next, as shown in (■) in the same figure, a nitride film 3 is provided on the surface of the element formation region, and polycrystalline silicon 4 that will become a gate electrode is further provided on this surface, and then silicon is deposited using photolithography technology. , the polycrystalline silicon 4 is selectively removed and patterned.

Next, arsenic atoms are ion-implanted into the P-well 9 through the gate oxide film 3 to form a Nu diffusion layer 5.5 which will become the source and drain of the N-channel transistor, and then into the semiconductor substrate 1. By ion-implanting hydrogen atoms, P-type diffusion regions 10, 10 which will become the source and drain of the P-channel transistor are formed.

After that, as shown in FIG. 6(C), a thick oxide film 6 that will become an IIT film is provided on the entire surface by the CVD method, and then the oxide film 6 and the gate oxide film 3 provided below are formed. A contact hole 7 is formed by opening the contact hole 7 by photolithography.

Next, heat treatment is performed for 15 minutes in a dry oxygen atmosphere at 1000°C to oxidize the surfaces of the N-type diffusion layer 5 and the P-diffusion layer 10 through the contact hole 7, and excessive vacancies are introduced due to the OED effect. As shown in Figure (2), the depth of the area is about 0.3% compared to the area covered with thick IIIt oxide.
It became μmR.

Next, after removing the oxide 11 formed on the surfaces of the N-type diffusion layer 5 and the P diffusion layer 10 in the oxidation process, aluminum was vapor-deposited as a wiring material 8 over the entire surface, as shown in Figure (6). After that, the CMO8 semiconductor device is fabricated by patterning using photolithography technology to make electrical contact.

Therefore, according to the above method, a part of the diffusion layer 5.10 is formed deeply by re-diffusing the OED effect red in the oxidized surrounding atmosphere, so that the inner diffusion layer 5.10 of the N type and P type is formed deeply. It can be formed deeply at the same time, and impurities of different conductive types can be introduced separately by aligning the masks twice as in the past.
It is easier to work with than the method of spreading with a ladle.

By forming the diffusion Wi5*IO deeply in the vicinity of the loose contact hole 7, it also spreads in the lateral direction of the diffusion layers 5 and 101d, thereby avoiding the risk of short-circuiting between the wiring material 8 and the semiconductor substrate 1. As a result, a large amount of compensation can be provided for the positional deviation between the contact hole 7 and the diffusion MS and tO, so that the amount of overlap can be reduced and high-density integration can be achieved.

Furthermore, since the diffusion layer 5.10 near the contact hole 2 is formed deeply, even if the aluminum used as the wiring material forms a sufficient eutectic with the semiconductor substrate 1, there will be no short-circuit, and the contact portion will not be short-circuited. It also has excellent reliability.

FIG. 3 shows another embodiment of the present invention, and the steps up to opening the contact hole 7 in the thick oxide film 6 are the same as those shown in FIG. 2 (4) to C). be.

Contact: After opening the hole 7, as shown in FIG. 3, a polycrystalline silicon layer I2 containing no impurities is deposited to a thickness of 500 Å over the entire surface.

Next, by low-temperature wet oxidation at 850°C, the polycrystalline silicon layer 12 is oxidized, and the N-type and P-type diffusion layers 5 are further formed in contact with the polycrystalline silicon layer 12 embedded in the contact hole 7.
．． 10 is also oxidized, and from 0ED9jJ onward, it proliferates and diffuses only in the vicinity of the multi-contact hole 7 and is formed deeply, resulting in the state shown in FIG.

Next, the oxidized polycrystalline silicon layer 12 and the diffusion layer 5+I
After removing the oxide 11 formed on the surface of the oxide, a wiring material 8 is deposited and further patterned to manufacture a CMO8 semiconductor device.

This method uses the oxidation of the polycrystalline silicon layer I2 to diffuse r@
Since 5.10 is oxidized, less portion of the diffusion layer 5.10 is oxidized, and a more reliable electrical contact can be obtained.

As explained above, according to the method for manufacturing a semiconductor device according to the present invention, even in the 0MO8 structure, re-diffusion into the diffusion layer is performed without the need for mask alignment, and a deep diffusion layer can be formed only in the vicinity of the contact hole, thereby improving workability. It has remarkable effects such as being excellent in terms of performance, enabling high-density integration, and having excellent reliability in contact areas.

[Brief explanation of drawings]

Figures 1(4) to 1(D) show MOS
FIG. 2 is a cross-sectional view sequentially showing the steps of manufacturing a semiconductor device.
5) to (6) of the same figure show CMO8 according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view sequentially showing the steps of manufacturing a semiconductor device.
G) and 03) are CMO8 according to other embodiments of the present invention.
FIG. 3 is a cross-sectional view sequentially illustrating the process of installing a wire body device and a metal body device. 1... Semiconductor substrate, 2... Field oxide film, 3...
...Gate oxide film, 4...Polycrystalline silicon, 5...
Diffusion layer, 6... Oxide film, 7... Contact hole, 8... Wiring material, 9... P well, 10... Diffusion layer, 1...
...Electric material, 12... Polycrystalline silicon layer.

Claims (5)

[Claims] (1) A step of providing an insulating film on the upper surface of a diffusion layer formed on the surface of a semiconductor substrate, a step of opening a contact hole in this insulating film, a step of oxidizing the diffusion layer through this contact hole,
Manufacturing a semiconductor device comprising the steps of removing oxide formed on the surface of the diffusion layer, and providing a wiring material on the entire surface and making electrical contact with the diffusion layer through a contact hole. Method. (2) The diffusion layer is 0 in which an N-type diffusion layer and a P-type diffusion layer are arranged side by side.
Claim 1 characterized in that it has an MO8 structure.
A method for manufacturing a semiconductor device according to section 1. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion layer is formed by molding either an N-type diffusion layer or a P-type diffusion layer. (4) The method for manufacturing a semiconductor device according to claim 1, wherein heat treatment is performed in a dry oxygen atmosphere as a method of oxidizing the diffusion layer. (5) The method of oxidizing the diffusion layer is performed by providing polycrystalline silicon on the contact leg and oxidizing it. ! A method for manufacturing a semiconductor device according to 1.