JPS5855345A - Glass composition for use in semiconductor device - Google Patents

Glass composition for use in semiconductor device

Info

Publication number
JPS5855345A
JPS5855345A JP15360981A JP15360981A JPS5855345A JP S5855345 A JPS5855345 A JP S5855345A JP 15360981 A JP15360981 A JP 15360981A JP 15360981 A JP15360981 A JP 15360981A JP S5855345 A JPS5855345 A JP S5855345A
Authority
JP
Japan
Prior art keywords
glass
range
composition
crystals
zno
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15360981A
Other languages
Japanese (ja)
Inventor
Yutaka Misawa
三沢 豊
Masaaki Takahashi
正昭 高橋
Katsuhiko Shioda
塩田 勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15360981A priority Critical patent/JPS5855345A/en
Publication of JPS5855345A publication Critical patent/JPS5855345A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00Glass compositions
    • C03C3/04Glass compositions containing silica
    • C03C3/062Glass compositions containing silica with less than 40% silica by weight
    • C03C3/064Glass compositions containing silica with less than 40% silica by weight containing boron
    • C03C3/066Glass compositions containing silica with less than 40% silica by weight containing boron containing zinc

Abstract

PURPOSE:To obtain a glass composition for use in a semiconductor device improved in fluctuation of a glass film, by mixing a glass of ZnO-B2O3-SiO2 in the range of depositing coarse crystals with those in the range of depositing fine crystals. CONSTITUTION:A glass of ZnO-B2O3-SiO2 type in the range of depositing fine crystals as shown in B of the figure is mixed with a glass in the range of depositing coarse crystals shown in A in 1:100-1:2. Said mixing ratio is determined by the following method: The glass depositing coarse crystals almost centering in the range A contg. 64wt% ZnO, 30wt% B2O3, and 6wt% SiO2 and the glass almost centering in the range B for depositing fine crystals contg. 67wt% ZnO, 22wt% B2O3, and 11wt% SiO2 are prepared, respectively, and it was found that it is necessary to control the mixing ratio of them in 0.01-0.5 in order to deposit fine crystals.

Description

【発明の詳細な説明】 本発明は半導体装置の表面安定化に適したガラス組成物
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a glass composition suitable for surface stabilization of semiconductor devices.

半導体装置特に半導体基体は、その表面が活性で外部か
らの有害物質例えばアルカリ金属や水分等によシ表面が
汚染されたり、悪影響を受は易く、その結果電気特性が
不安定、特性の劣化を招くことが多い。これを防止する
ために、半導体基体表面を、半導体酸化物、半導体窒化
物、金属酸化物或いは有機物で被覆することが行なわれ
ている。
Semiconductor devices, especially semiconductor substrates, have active surfaces and are easily contaminated or adversely affected by external harmful substances such as alkali metals and moisture, resulting in unstable electrical characteristics and deterioration of characteristics. Often invited. In order to prevent this, the surface of the semiconductor substrate is coated with a semiconductor oxide, a semiconductor nitride, a metal oxide, or an organic substance.

また、最近同様な目的のために粉末を焼付けたガラス膜
が注目されている。ガラス膜は、半導体酸化物、半導体
窒化物、金属酸化物及び有機物に比較して、気体、液体
の透過に対して優れた阻止効果を有することから表面安
定化膜として適している。ガラス膜を半導体装置の表面
安定化膜として使用するためには、(1)熱膨張係数が
半導体のそれにできるだけ近いこと、(2)高温、高電
界で電気的に安定なこと、(3)アルカリ金属等の有害
な不純物を含まないこと、(4)適当な表面電荷密度(
Nrs)を有すること、等が要求される。これらの要求
を満すガラスとして、Z n OB2O3S 10x 
 を主成分とする結晶質ガラスが知られている。しかし
ながらこのzno−B2o、−s io、  を主成分
とする結晶質ガラスを使用した場合、次のような問題の
あることがわかった。即ち、結晶質ガラスは、その組成
によって結晶粒の大きな粗大結晶となったシ、結晶粒の
小さい微細結晶となシ、その結晶粒の大きさによシガラ
ス膜の特性が変動することである。例えば、結晶粒が大
きくなる組成のガラスは、負で大きい値のNFI+  
を有し高耐圧の半導体装置特にチャンネルカットを有す
る半導体装置に適したガラスであるが、結晶粒が大きて
ために洩れ電流が多くなシ高耐圧の半導体装置に適用で
きなくなる。
Recently, glass films made of baked powder have been attracting attention for similar purposes. A glass film is suitable as a surface stabilizing film because it has an excellent blocking effect against gas and liquid permeation compared to semiconductor oxides, semiconductor nitrides, metal oxides, and organic substances. In order to use a glass film as a surface stabilizing film for semiconductor devices, it must (1) have a thermal expansion coefficient as close as possible to that of a semiconductor, (2) be electrically stable at high temperatures and high electric fields, and (3) be alkali-based. Contains no harmful impurities such as metals, (4) Appropriate surface charge density (
Nrs), etc. As a glass that meets these requirements, Z n OB2O3S 10x
Crystalline glass whose main component is However, when this crystalline glass containing zno-B2o, -sio, as a main component was used, it was found that the following problems occurred. That is, depending on the composition of crystalline glass, it may be coarse crystals with large crystal grains or fine crystals with small crystal grains, and the characteristics of the glass film vary depending on the size of the crystal grains. For example, a glass with a composition that increases the size of crystal grains has a negative and large value of NFI+
Although this glass is suitable for semiconductor devices with high breakdown voltages, especially semiconductor devices with channel cuts, it cannot be applied to semiconductor devices with high breakdown voltages, which have large crystal grains and have a large amount of leakage current.

本発明の目的は、上述の問題点を除去し半導体装置の表
面安定化に適したガラス組成物を提供することにある。
An object of the present invention is to provide a glass composition that eliminates the above-mentioned problems and is suitable for surface stabilization of semiconductor devices.

か\る目的を奏する本発明半導体装置用ガラス組成物の
特徴とするところは、ZnOBtus−8iO2系の粗
大結晶を析出する範囲の組成のガラスに、Z”OBt0
3 5t02系の微細結晶を析出する範囲のガラスを1
00:1〜2:1の割合で混合した点にある。具体的に
は、第1図のZn0Btus  5jOt三元組成図の
Aで示す範囲の組成のガラスに、Bで示す範囲の組成の
ガラスを100:1〜2:1混合したガラス組成物であ
る。
The glass composition for semiconductor devices of the present invention that achieves the above purpose is characterized by adding Z"OBt0
3 Glass in the range where 5t02-based fine crystals are precipitated is 1
The point is that they were mixed at a ratio of 0.00:1 to 2:1. Specifically, it is a glass composition in which a glass having a composition in the range indicated by A in the Zn0Btus 5jOt ternary composition diagram in FIG. 1 is mixed with a glass having a composition in the range indicated by B in a ratio of 100:1 to 2:1.

第1図の曲線で包囲された部分は均質な結晶質ガラスが
得られる組成範囲を示し、そのうち人で示された部分は
結晶化した場合第2図(a)に示すような結晶粒の大き
い粗大結晶を析出する組成範囲を、Bで示された部分は
結晶化した場合第2図の)に示すような結晶粒の小さい
微細結晶を析出する組成範囲を、それぞれ示す。本発明
は、粗大結晶を析出するガラスに微細結晶を析出するガ
ラスを適当量混合することにょシ、粗大結晶を析出する
ガラスの特性を保持したま\機構結晶を析出することが
できるという発見に基づいてなされたものである。
The area surrounded by the curve in Figure 1 shows the composition range in which a homogeneous crystalline glass can be obtained, and the area indicated by the figure shows the large crystal grains as shown in Figure 2 (a) when crystallized. The composition range in which coarse crystals are precipitated is shown, and the part indicated by B is the composition range in which fine crystals with small crystal grains as shown in FIG. 2 are precipitated when crystallized. The present invention is based on the discovery that by mixing an appropriate amount of glass that precipitates fine crystals with glass that precipitates coarse crystals, it is possible to precipitate mechanical crystals while retaining the properties of glass that precipitates coarse crystals. This was done based on the following.

微細結晶を析出するガラスの混合量は次のようにして定
めた。粗大結晶を析出する組成範囲のうちの略中夫に位
置するZnO:64重量%。
The mixing amount of glass to precipitate fine crystals was determined as follows. ZnO: 64% by weight, located approximately in the middle of the composition range in which coarse crystals are precipitated.

B20  : 3o重量%、5i02 : L重t%O
カラxと、微細結晶を析出する範囲のうち略中夫に位置
するZnO:67重量%、Btus : 22重量%。
B20: 3o weight%, 5i02: L weight t%O
ZnO: 67% by weight, Btus: 22% by weight, located approximately in the middle of the range where fine crystals are precipitated.

8”Ot : 11重量%のガラスを準備し、これらの
混合比を順次変え、その時のNFB及び洩れ電流を測定
した。その結果を表1に示す。
8"Ot:11% by weight glass was prepared, the mixing ratio of these was changed sequentially, and the NFB and leakage current were measured. The results are shown in Table 1.

表1によれば、微細結晶を析出するガラスの混合比が0
.01を越えると、混合ガラスは微細結晶を析出するよ
うになシ、洩れ電流をIX 10−7(A)以下となシ
、混合比が0,5を越えるとN P B が−4X 1
0 ” 7cm”から−I X 10 ”7cm2と急
増する。NF!+ が正に近づくと空乏層の拡がシが悪
くなシ耐圧が低下する。従って、微細結晶を析出するガ
ラスの混合比は、0.01〜0.5にする必要がある。
According to Table 1, the mixing ratio of glass that precipitates fine crystals is 0.
.. If the mixing ratio exceeds 0.01, fine crystals will precipitate in the mixed glass, and the leakage current must be kept below IX 10-7 (A). If the mixing ratio exceeds 0.5, N P B will become -4X 1.
It rapidly increases from 0 ``7cm'' to -I , 0.01 to 0.5.

次に、本発明のガラス組成物で表面安定化処理し九半導
体装置を例に採って本発明の詳細な説明する。
Next, the present invention will be explained in detail by taking as an example a nine semiconductor device which has been subjected to surface stabilization treatment using the glass composition of the present invention.

第3図は、一方の主表面にガラスで被覆された環状溝を
有するモート形のゲートターンオフサイリスタを示して
いる。図において、1は互いに反対側に位置する一対の
主表面11,12、一方の主表面11の周辺付近に形成
された環状溝13、一対の主表面間に連続して形成され
たNエミッタ領域N鳶、Pペース領域Pg、Nペース領
域Nm及びPエミッタ領域Pgを具備する半導体基体で
ある。Nエミッタ領域Niは一方の主表面11の一部に
露出するように形成され、Pベース領域PRはNエミッ
タ領域Ni、に隣接して第1のPN接合J、を形成し、
環状溝13よシ浅い深さを有し表面が一方の主表面11
及び環状溝13に露出するように形成されている。Nベ
ース領域NilはPベース領域PRに隣接して環状溝1
3に端部が露出する第2のPN接合J2を形成する高抵
抗部Ns−と、一方の主表面11の環状溝13の外周側
及び他方の主表面12に霧出する低抵抗部NB+とから
成っている。Pエミッタ領域P、xFiNベース領域N
領域N液しNペース領域NBとの間に第3のPN接合J
、を形成し、一方の主表面11へ投影した時一部がNエ
ミッタ領域Niと重なシ、他方の主表面12へ露出する
ように形成されている。
FIG. 3 shows a moat-shaped gate turn-off thyristor with a glass-covered annular groove on one major surface. In the figure, reference numeral 1 denotes a pair of main surfaces 11 and 12 located on opposite sides, an annular groove 13 formed near the periphery of one main surface 11, and an N emitter region continuously formed between the pair of main surfaces. This is a semiconductor substrate comprising an N pass region, a P pace region Pg, an N pace region Nm, and a P emitter region Pg. The N emitter region Ni is formed to be exposed on a part of one main surface 11, the P base region PR forms a first PN junction J adjacent to the N emitter region Ni,
The main surface 11 has a shallower depth than the annular groove 13 and has one surface.
and is formed so as to be exposed to the annular groove 13. The N base region Nil is adjacent to the P base region PR in the annular groove 1.
3, a high resistance part Ns- forming a second PN junction J2 whose end is exposed at It consists of P emitter region P, xFiN base region N
Third PN junction J between region N liquid and N pace region NB
, and are formed so that when projected onto one main surface 11, a portion thereof overlaps with the N emitter region Ni and is exposed onto the other main surface 12.

2は一方の主表面11においてNエミッタ領域Nmの露
出面に接触した一方の主電極、3は他方の主表面12に
おいてPエミッタ領域P1及びNペース領域NBの露出
面に接触した他方の主電極、4は一方の主表面11にお
いてPベース領域P1の露出面に接触した制御電極、5
は一方の主表面11の残部を被覆する半導体酸化膜、6
は環状溝13の表面に被着したガラス膜である。このガ
ラス膜6は、ZnO:64重量%、B20.:30重蓋
%、5io2: 6重量%からなる粗大結晶を析出する
ガラス粉末と、ZnO:67重量%、 B2us:22
重量%、5in2二11重量%からなる微細結晶を析出
するガラス粉末とを95:5の混合比で混合したものを
電気泳動法で環状溝13表面に付着し、焼成したもので
ある。
2 is one main electrode that is in contact with the exposed surface of the N emitter region Nm on one main surface 11, and 3 is the other main electrode that is in contact with the exposed surfaces of the P emitter region P1 and the N pace region NB on the other main surface 12. , 4 is a control electrode in contact with the exposed surface of the P base region P1 on one main surface 11;
6 is a semiconductor oxide film covering the remainder of one main surface 11;
is a glass film adhered to the surface of the annular groove 13. This glass film 6 contains ZnO: 64% by weight, B20. : 30% by weight, 5io2: 6% by weight of glass powder that precipitates coarse crystals, ZnO: 67% by weight, B2us: 22
A glass powder which precipitates fine crystals of 5 in 2 - 11 weight % by weight was mixed at a mixing ratio of 95:5 and adhered to the surface of the annular groove 13 by electrophoresis and fired.

か\る構成のゲートターンオフサイリスタの耐圧分布は
第4図(C)に示すように極めて優れている。
The gate turn-off thyristor having such a configuration has an extremely excellent breakdown voltage distribution as shown in FIG. 4(C).

因に、第3図と同一構成でガラス膜6を粗大結晶を析出
するガラスのみで形成した場合及び微細結晶を析出する
ガラスのみで形成した場合の耐圧分布をそれぞれ第4図
(a)及び(b)に示す。図から明らかな如く、粗大結
晶を析出するガラスのみでは耐圧のばらつきが大きく、
微細結晶を析出するガラスのみでは耐圧が低くなる。こ
のように、本発明ガラス組成物を半導体装置の表面安定
化膜に使用すれば、高耐圧の半導体装置を高歩留を得る
ことができる。
Incidentally, FIGS. 4(a) and 4(a) show the breakdown voltage distributions when the glass film 6 is formed only from glass that precipitates coarse crystals and when it is formed only from glass that precipitates fine crystals with the same configuration as in FIG. 3, respectively. Shown in b). As is clear from the figure, with only glass that precipitates coarse crystals, there is a large variation in breakdown voltage.
Glass that precipitates fine crystals only has a low breakdown voltage. As described above, when the glass composition of the present invention is used for a surface stabilizing film of a semiconductor device, a high yield of semiconductor devices with high breakdown voltage can be obtained.

本発明のガラス組成物はゲートターンオフサイリスタに
限らずダイオード、トランジスタ、サイリスタのいずれ
にも適用でき、半導体基体の形状も、モート形に限らず
プレーナ形、メサ形、ベベル形のいずれにも適用できる
。なかでも、本発明ガラス組成物の効果をより発揮でき
るのは、第3図の一方の主表面11の環状溝13の外周
側に設けられたNB+部分の如く、空乏層の拡がりをN
”層で阻止するいわゆるチャンネルストツノく領域を具
備する半導体装置である。
The glass composition of the present invention can be applied not only to gate turn-off thyristors but also to diodes, transistors, and thyristors, and the shape of the semiconductor substrate is not limited to moat shape but can also be applied to planar, mesa, and bevel shapes. . Among these, the effect of the glass composition of the present invention can be more effectively achieved when the spread of the depletion layer is reduced by N, as in the NB+ portion provided on the outer peripheral side of the annular groove 13 on one main surface 11 in FIG.
This is a semiconductor device having a so-called channel blocking region blocked by a layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のガラス組成物を説明するための三元組
成図、第2図はガラス組成物の顕微鏡写真による拡大図
、第3図は本発明ガラス組成物を使用した半導体装置の
概略断面図、第4図は本発明ガラス組成物及び従来のガ
ラス組成物を半導体装置に適用した場合の耐圧分布図で
ある。 1・・・半導体基体、6・・・ガラス膜、13・・・環
状溝。 @1m 5rOz(◆」1%) (b)
Figure 1 is a ternary composition diagram for explaining the glass composition of the present invention, Figure 2 is an enlarged micrograph of the glass composition, and Figure 3 is a schematic diagram of a semiconductor device using the glass composition of the present invention. The cross-sectional view and FIG. 4 are breakdown voltage distribution diagrams when the glass composition of the present invention and the conventional glass composition are applied to a semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 6... Glass film, 13... Annular groove. @1m 5rOz (◆”1%) (b)

Claims (1)

【特許請求の範囲】 1、半導体装置の少なくともPN接合露出端を被覆する
zno  B2O3S 102  系ガ、Fスであって
、第1図の人で示す範囲の組成のガラスに、Bで示す範
囲の組成のガラスを100二1〜2:・1混合し次こと
を特徴とする半導体装置用ガラス組成物。 2、特許請求の範囲第1項において、第1図の人で示す
範囲の組成のガラスは粗大結晶を析出するガラス、Bで
示す範囲の組成のガラスは微細結晶を析出するガラスで
あることを特徴とする半導体装置用ガラス組成物。
[Scope of Claims] 1. Zno B2O3S 102 series glass, which covers at least the exposed end of the PN junction of a semiconductor device, is a glass having a composition in the range indicated by the figure in FIG. 1. A glass composition for a semiconductor device, which is obtained by mixing glasses having a composition of 10021 to 2:.1 and having the following characteristics. 2. In claim 1, it is stated that the glass with the composition in the range indicated by the figure in FIG. Characteristic glass composition for semiconductor devices.
JP15360981A 1981-09-30 1981-09-30 Glass composition for use in semiconductor device Pending JPS5855345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15360981A JPS5855345A (en) 1981-09-30 1981-09-30 Glass composition for use in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15360981A JPS5855345A (en) 1981-09-30 1981-09-30 Glass composition for use in semiconductor device

Publications (1)

Publication Number Publication Date
JPS5855345A true JPS5855345A (en) 1983-04-01

Family

ID=15566221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15360981A Pending JPS5855345A (en) 1981-09-30 1981-09-30 Glass composition for use in semiconductor device

Country Status (1)

Country Link
JP (1) JPS5855345A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193238A (en) * 1984-10-15 1986-05-12 Mitsubishi Electric Corp Suction device for engine
WO2013168236A1 (en) * 2012-05-08 2013-11-14 新電元工業株式会社 Resin-sealed semiconductor device and production method for resin-sealed semiconductor device
JP5827398B2 (en) * 2012-05-08 2015-12-02 新電元工業株式会社 Method for manufacturing glass composition for protecting semiconductor junction, method for manufacturing semiconductor device, and semiconductor device
JPWO2013168623A1 (en) * 2012-05-08 2016-01-07 新電元工業株式会社 Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device
DE102017103863A1 (en) 2016-03-30 2017-10-05 Mitsubishi Electric Corporation Control unit and control method for an internal combustion engine
DE102016215896B4 (en) 2016-01-18 2020-06-18 Mitsubishi Electric Corporation Control and control procedures for internal combustion engines

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193238A (en) * 1984-10-15 1986-05-12 Mitsubishi Electric Corp Suction device for engine
WO2013168236A1 (en) * 2012-05-08 2013-11-14 新電元工業株式会社 Resin-sealed semiconductor device and production method for resin-sealed semiconductor device
JP5827398B2 (en) * 2012-05-08 2015-12-02 新電元工業株式会社 Method for manufacturing glass composition for protecting semiconductor junction, method for manufacturing semiconductor device, and semiconductor device
JP5827397B2 (en) * 2012-05-08 2015-12-02 新電元工業株式会社 Resin-sealed semiconductor device and method for manufacturing resin-sealed semiconductor device
JPWO2013168623A1 (en) * 2012-05-08 2016-01-07 新電元工業株式会社 Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device
DE102016215896B4 (en) 2016-01-18 2020-06-18 Mitsubishi Electric Corporation Control and control procedures for internal combustion engines
DE102017103863A1 (en) 2016-03-30 2017-10-05 Mitsubishi Electric Corporation Control unit and control method for an internal combustion engine

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