KR19990076245A - Planer-type triac element and manufacturing method thereof - Google Patents

Abstract

A planar triac device and a method of manufacturing the same according to the present invention include a lower electrode, a p-type first semiconductor layer and an n-type second semiconductor layer sequentially formed on the lower electrode, and the second semiconductor layer. A p-type third semiconductor layer formed, an n-type fourth semiconductor layer formed in the first semiconductor layer, a p-type device isolation region formed over the first and second semiconductor layers, and the third semiconductor layer A p-type field limiting ring formed in the second semiconductor layer between the device isolation region and the device isolation region, an n-type fifth semiconductor layer formed in the third semiconductor layer, and an upper portion connected to the third and fifth semiconductor layers. It is composed of electrodes. 1) By using electric field limiting ring, it is possible to alleviate the electric field of the surface blocking voltage and the back blocking voltage at the same time. Therefore, it is possible to prevent the lowering of the back blocking voltage caused by the surface state instability. Of being able to improve the overall cut-off voltage characteristic, 2) Because of this, since the channel stopper is not required it is possible to also minimize the overall size of the device.

Description

Planer-type triac element and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional device and a method of manufacturing the same, and more particularly, to a planar triac device and a method for effectively controlling the bidirectional blocking voltage of a planar triac device applied to a medium and small capacity device. It relates to a manufacturing method.

Since the triac element is a kind of thyristors, bidirectional control is possible, and thus the blocking voltage characteristic has two operating modes (for example, a surface breaking voltage mode and a back breaking voltage mode), and is mainly used as an AC switch.

The device has various forms according to the cut-off voltage and current rating. Representative examples thereof include a double-sided mesa-type triac element, a single mesa-triac element and a planar triac element. Can be.

The double, double-sided mesa type and single mesa type triac are useful structures in high breakdown voltage devices of 1000V or more, and the voltage control is advantageous because the surface breakdown voltage and the backside breakdown voltage appear as the plane breakdown voltage.

However, the triac of the mesa-type structure is not only required to stabilize the process progress when manufacturing the device, but also due to the low blocking voltage efficiency of the device is limited to a wide range of applications, and in the case of medium and small-capacity devices as a limitation in the process progress Due to the disadvantage that it is very difficult to manufacture a small size mesa structure, planar triac structure is generally used in the manufacture of medium and small-capacity bidirectional devices.

Figure 1 is a cross-sectional view showing the structure of a conventional planar triac device applied to the medium and small capacity devices associated with it.

Referring to the cross-sectional view, in the conventional planar triac device, the p-type first semiconductor layer 16 and the n-type second semiconductor layer 10 which act as gates on the lower electrode 28 are sequentially arranged. A p + type isolation region 14 is formed over the first and second semiconductor layers 16 and 10, and a p type serving as a gate in the second semiconductor layer 10 is formed. A third semiconductor layer 18 is formed, and an n + type fourth semiconductor layer 22 serving as a cathode is formed in the first semiconductor layer 16 to contact the lower electrode 28. In the third semiconductor layer 18, a n + type fifth semiconductor layer 26 serving as a cathode is formed to contact the upper electrode 30, and the device isolation region 14 and the third semiconductor layer 18 are formed. In the second semiconductor layer 10 therebetween, a p-type field limited ring 20 is formed to contact the insulating layer 12 to limit the electric field. In the second semiconductor layer 10 between the device isolation region 14 and the field limiting ring 20, an n + type channel stopper 24 is connected to the insulating layer 12 to reduce the surface current. It can be seen that is configured to have a formed structure. In this case, the channel stopper 24 is configured to have the same junction depth as the fifth semiconductor layer 26, and the field limiting ring 20 is configured to have the same junction depth as the third semiconductor layer 18.

2 shows a plan view from above of the planar triac element of the structure. According to the plan view, a channel stopper 24 having a predetermined width and the field limiting ring 20 are predetermined in the same plane in the second semiconductor layer 10 between the device isolation region 14 and the third semiconductor layer 18. It can be seen that the lines are arranged along the outer portion of the third semiconductor layer 18 in a spaced apart state.

In this way, the field limiting ring 20 is formed in the second semiconductor layer 10 between the device isolation region 14 and the third semiconductor layer 18. Since it can be approximated by the breakdown voltage applied to the plane junction, no special consideration is required in manufacturing the device. However, in the case of the surface breaking voltage, when the breakdown voltage of the device is determined in the radius of curvature of the third semiconductor layer 18, This is to prevent the phenomenon that the efficiency of the surface blocking voltage is limited by the curvature electric field of the p-type gate, which is a semiconductor layer.

However, when the planar triac device is manufactured to have the above structure, several problems occur as follows.

First, in order to reduce the amount of leakage current generated on the surface of the silicon substrate (for example, the n-type second semiconductor layer), the device isolation region 14 and the electric field limit in the second semiconductor layer 10 during triac manufacturing. Since the channel stopper 24 should be formed so as to be spaced apart from the ring 20 by a predetermined interval (for example, about 110 μm), this causes an increase in the overall size of the device.

Second, in general, the planar triac device has a structure in which the breakdown voltages applied to the surface and the back surface are determined according to the surface state of the device. In the triac device shown in FIG. However, when a large amount of impurities (eg, Na, Fe, etc.) as a charge component are contained in the insulating layer 12 due to a process progression problem, the surface state of the device becomes unstable and the device isolation region 14 The phenomenon that the electric field is concentrated in the ⓐ part of) occurs. As such, when the electric field is concentrated on the part ⓐ, the backside blocking voltage decreases, thereby causing a phenomenon in which the overall breaking voltage characteristic of the triac device is deteriorated. Therefore, there is an urgent need for improvement.

Accordingly, an object of the present invention is to provide a planar triac device capable of minimizing the overall size of the device while preventing degradation of the blocking voltage characteristic caused by electric field concentration at the part ⓐ.

Another object of the present invention is to provide a manufacturing method that can effectively manufacture the planar triac device.

1 is a cross-sectional view showing the structure of a conventional planar triac device;

2 is a plan view from above of the cross-sectional view of FIG. 1;

3 is a cross-sectional view showing the structure of a planar triac device according to the present invention;

4 is a plan view from above of the cross-sectional view of FIG. 3;

5A to 5C are process flowcharts illustrating a method of manufacturing a planar triac device shown in FIG. 3.

In the present invention, a lower electrode; A p-type first semiconductor layer and an n-type second semiconductor layer sequentially formed on the lower electrode; A third p-type semiconductor layer formed in said second semiconductor layer; An n-type fourth semiconductor layer formed in the first semiconductor layer; A p-type isolation region formed over the first and second semiconductor layers; A p-type field limiting ring formed in said second semiconductor layer between said third semiconductor layer and said device isolation region; An n-type fifth semiconductor layer formed in the third semiconductor layer; And an upper electrode connected to the third and fifth semiconductor layers.

In order to achieve the above object, the present invention provides a method for forming a semiconductor device, comprising: forming a p-type isolation region in a predetermined portion of an n-type semiconductor substrate; Forming a p-type first semiconductor layer inside one surface of the substrate; Simultaneously forming a p-type electric field limiting ring and a p-type third semiconductor layer inside the other side of the substrate using an optional impurity diffusion process; Forming an n-type fourth semiconductor layer inside the first semiconductor layer; Forming an n-type fifth semiconductor layer in the third semiconductor layer; Forming a lower electrode connected to the first and fourth semiconductor layers; And a step of forming an upper electrode connected to the third and fifth semiconductor layers. Here, the semiconductor substrate is regarded as an n-type second semiconductor layer.

When the planar triac device is manufactured to have the above structure, the electric field of the surface blocking voltage and the back blocking voltage can be alleviated at the same time by using the electric field limiting ring, thereby preventing the blocking voltage characteristic from deteriorating. As a result, it is not necessary to form a channel stopper to reduce the surface leakage current, so that the overall size of the device can also be made smaller than in the conventional case.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, an electric field limiting ring is formed in the second semiconductor layer between the device isolation region and the third semiconductor layer to simultaneously alleviate the electric field of the surface blocking voltage and the back blocking voltage. By preventing the backside blocking voltage from being reduced, the technique focused on improving the overall breaking voltage characteristics of the planar triac device, which will be described in detail with reference to the drawings shown in FIGS. Same as

3 is a cross-sectional view showing the structure of the planar triac device shown in the present invention, Figure 4 is a plan view looking down from the cross-sectional view of Figure 3, Figures 5a to 5c is a planar type shown in Figure 3 The process purity which shows the manufacturing method of a triac element is shown.

Referring to FIG. 3, the planar triac device applied to the medium and small capacity devices proposed in the present invention is large, and the p-type first semiconductor layer 106 and the n-type gate act as gates on the lower electrode 116. The second semiconductor layer 100 is sequentially stacked, and a p + type device isolation region 104 is formed over the first and second semiconductor layers 106 and 100, and the second semiconductor layer ( A p-type third semiconductor layer 110 acting as a gate is formed in 100, and an n + -type fourth semiconductor acting as a cathode to contact the lower electrode 116 in the first semiconductor layer 106. A layer 112 is formed, and an n + type fifth semiconductor layer 114 serving as a cathode is formed in the third semiconductor layer 110 to contact the upper electrode 118, and the device isolation region 104 is formed. In the second semiconductor layer 100 between the third semiconductor layer 110 and the third semiconductor layer 110 to contact the insulating layer 102 to limit the electric field. It can be seen that the field limit ring 108 is configured to have a formed structure. In this case, the field limiting ring 108 is configured to have the same junction depth as that of the third semiconductor layer 110.

In the case of configuring the device as described above, the electric field limiting ring 108 formed between the device isolation region 104 and the third semiconductor layer 110 serves to alleviate the electric field of the surface blocking voltage and the back blocking voltage at the same time. Even if the electric field is concentrated in the ⓐ part due to surface state instability, it can be alleviated by using the electric field limiting ring 108, thereby preventing the backside blocking voltage from being reduced due to electric field concentration. In addition, since it is not necessary to form a separate channel stopper for preventing the surface leakage current, it is possible to minimize the overall size of the device.

4 shows a plan view from above of the planar triac element of the structure. According to the plan view, it can be seen that the field limit ring 108 is disposed in the second semiconductor layer 100 between the device isolation region 104 and the third semiconductor layer 110 so as to be spaced apart from each other by a predetermined distance. .

Therefore, the triac element having the above structure is manufactured based on the following process sequence, as can be seen from the process sequence diagram shown in FIGS. 5A to 5C. For convenience, this will be described by dividing it into a third step.

As a first step, as shown in FIG. 5A, an insulating layer 102 made of an oxide film is formed on the front side and the back side of the n-type semiconductor substrate 100, and chemical source deposition ( Chemical source deposition (hereinafter referred to as a CSD) method is used to inject a p-type source (for example, B) into the substrate 100 and diffuse it to form a p-type device isolation region ( 104). At this time, the p-type source is injected in both the front and back surface of the substrate. In this way, the device isolation region 104 is formed by the CSD method because the thickness of the insulating layer 102 is about 20,000 [mu] s, which makes it difficult to apply the impurity ion implantation process.

The device isolation region forming process using the CSD method is performed through the following steps (a) to (c), which will be described in detail below. As a step (a), the insulating layer 102 formed on the front and back surfaces of the substrate is partially selected and etched using a photolithography process so that the surface of the substrate 100 of the device isolation region forming unit is exposed. As a step (b), the p-type source is deposited on the front and back surfaces of the substrate 100 by CVD. In this process, the Si forming the source and the substrate 100 is substituted to obtain an effect of injecting a p-type source into the surface of the inside of the substrate 100. In step (c), an insulating layer 102 of an oxide film is selectively formed only on the surface exposed portion of the substrate 100, and a heat treatment is performed to form a p-type device isolation region 104 in the substrate 100. .

As a second step, as shown in FIG. 5B, the p-type impurity is entirely implanted into the back surface of the substrate 100 using the aforementioned CSD method to form the p-type first semiconductor layer 106 at the bottom of the substrate. In addition, p-type impurities are selectively implanted into the front surface of the substrate 100 to simultaneously form the third semiconductor layer 110 and the electric field limiting ring 108 at predetermined intervals on the upper end of the substrate. In this case, the field limiting ring 108 is formed between the device isolation region 104 and the third semiconductor layer 110. When the process is performed in this way, a result of the structure in which the first and third semiconductor layers 106 and 110 are placed on both surfaces with the substrate 100 interposed therebetween is provided. The substrate 100 is described as a second semiconductor layer at reference numeral 100.

As a third step, as shown in FIG. 5C, the n-type fourth semiconductor layer 112 to be connected to the lower electrode is formed in the first semiconductor layer 106 using the CSD method, and subsequently the third semiconductor layer ( An n-type fifth semiconductor layer 114 to be connected to the upper electrode is formed in the 110. Next, the isolation region 104 and the insulating layer 102 on the first and fourth semiconductor layers 106 and 112 are removed, and a lower electrode 116 is formed on the entire surface thereof, and then a photolithography process is performed. Selectively etching the insulating layer 102 formed on the front surface to expose the surface of the third and fifth semiconductor layer 110, 114 by a predetermined portion, and the third and fifth semiconductor layer 110, By forming the upper electrode 118 connected to the 114, the triac element fabrication is completed.

As described above, according to the present invention, 1) the electric field of the surface blocking voltage and the back blocking voltage can be alleviated at the same time by using the electric field limiting ring, so that even if the electric field is concentrated on the ⓐ part, The blocking voltage can be prevented from being reduced, thereby improving the overall blocking voltage characteristic of the planar triac device, and 2) thereby minimizing the overall size of the device since the channel stopper is not required.

Claims (2)

A lower electrode; A p-type first semiconductor layer and an n-type second semiconductor layer sequentially formed on the lower electrode; A third p-type semiconductor layer formed in said second semiconductor layer; An n-type fourth semiconductor layer formed in the first semiconductor layer; A p-type isolation region formed over the first and second semiconductor layers; A p-type field limiting ring formed in said second semiconductor layer between said third semiconductor layer and said device isolation region; An n-type fifth semiconductor layer formed in the third semiconductor layer; And And a top electrode connected to the third and fifth semiconductor layers. forming a p-type device isolation region in a predetermined portion of the n-type semiconductor substrate; Forming a p-type first semiconductor layer inside one surface of the substrate; Simultaneously forming a p-type electric field limiting ring and a p-type third semiconductor layer inside the other side of the substrate using an optional impurity diffusion process; Forming an n-type fourth semiconductor layer inside the first semiconductor layer; Forming an n-type fifth semiconductor layer in the third semiconductor layer; Forming a lower electrode connected to the first and fourth semiconductor layers; And And forming a top electrode connected to the third and fifth semiconductor layers.