JPH0582069B2 - - Google Patents
Info
- Publication number
- JPH0582069B2 JPH0582069B2 JP58015748A JP1574883A JPH0582069B2 JP H0582069 B2 JPH0582069 B2 JP H0582069B2 JP 58015748 A JP58015748 A JP 58015748A JP 1574883 A JP1574883 A JP 1574883A JP H0582069 B2 JPH0582069 B2 JP H0582069B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- tft
- insulating film
- semiconductor layer
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 64
- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 description 10
- 239000010407 anodic oxide Substances 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000005685 electric field effect Effects 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- NGPGDYLVALNKEG-UHFFFAOYSA-N azanium;azane;2,3,4-trihydroxy-4-oxobutanoate Chemical compound [NH4+].[NH4+].[O-]C(=O)C(O)C(O)C([O-])=O NGPGDYLVALNKEG-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- 229910052949 galena Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
Description
【発明の詳細な説明】
＜技術分野＞
本発明は絶縁ゲート形薄膜トランジスタ（以下
TFTと称す）に関するものであり、特に半導体
層に少なくとも一部が微結晶化したシリコン（以
下単に微結晶シリコンと称す）を用いた場合に於
いて、特性が良好で高い信頼性を得ることができ
るTFTの製造方法に関するものである。[Detailed Description of the Invention] <Technical Field> The present invention relates to an insulated gate thin film transistor (hereinafter referred to as
This technology relates to TFTs (hereinafter simply referred to as microcrystalline silicon), and in particular, when using at least partially microcrystalline silicon (hereinafter simply referred to as microcrystalline silicon) in the semiconductor layer, it is possible to obtain good characteristics and high reliability. The present invention relates to a method for manufacturing TFTs that can be produced.
＜従来技術＞
従来の一般的なTFTの構造及びその形成法に
ついて第１図とともに説明する。絶縁基板１上に
ゲート電極２、ゲート絶縁膜３、半導体層４を順
次堆積し、半導体層４にソース電極５及びドレイ
ン電極６を形成することによりTFTが作製され
る。絶縁基板１としては一般的にガラス板、セラ
ミツク板、石英板等が用いられる。また、ゲート
電極２はCr、Al、Ni、Au等の金属材料、ゲート
絶縁膜３はSiO、SiO2、Al2O3、Ta2O5、Y2O3、
Si3N4、M9F2等の酸化物、窒化物又は弗化物、
半導体層４はCdS、CdSe、Te、PbS、アモルフ
アスシリコン又は微結晶シリコン等で形成され
る。ソース電極５及びドレイン電極６としては
Al、Au、Ni、Cr、In等の半導体層４とオーミツ
クコンタクトが可能な金属が用いられる。<Prior Art> The structure of a conventional general TFT and its formation method will be explained with reference to FIG. A TFT is manufactured by sequentially depositing a gate electrode 2, a gate insulating film 3, and a semiconductor layer 4 on an insulating substrate 1, and forming a source electrode 5 and a drain electrode 6 on the semiconductor layer 4. As the insulating substrate 1, a glass plate, a ceramic plate, a quartz plate, etc. are generally used. Further, the gate electrode 2 is made of a metal material such as Cr, Al, Ni, or Au, and the gate insulating film 3 is made of SiO, SiO 2 , Al 2 O 3 , Ta 2 O 5 , Y 2 O 3 ,
Oxides, nitrides or fluorides such as Si 3 N 4 and M 9 F 2 ;
The semiconductor layer 4 is formed of CdS, CdSe, Te, PbS, amorphous silicon, microcrystalline silicon, or the like. As the source electrode 5 and drain electrode 6
A metal capable of making ohmic contact with the semiconductor layer 4, such as Al, Au, Ni, Cr, or In, is used.
上記構造を有するTFTを例えば液晶表示装置
のマルチブレツクス駆動に使用する場合、TFT
のオフ抵抗（ROFF）が充分に高く遮断性が良好で
あること、オン抵抗（RON）が充分に低くオン／
オフ比（ROFF／RON）が高いこと及びスイツチン
グ速度が大きいことを必要とし、更に長時間の動
作に対して安定であることが要求される。このよ
うな特性を満足するTFTを実現するためには
TFTのゲート絶縁膜３が、(1)絶縁性が良好（ピ
ンホールが無い）でかつ信頼性及び耐圧が高いこ
と、(2)可動イオン密度か低いこと、(3)半導体との
界面準位密度が小さいこと、(4)半導体に対する電
界効果が大きいこと、等の条件を満たしているこ
とが必要であるが、上記(1)と(4)は相反する要求で
ありこれを同時に満足させることは困難である。
例えば、スパツタリング法、CVD法等でSiO2、
Si3N4等の薄膜を形成する場合、2000〜3000Å以
下の厚さではピンホールの無い薄膜を形成するこ
とは極めて困難となる。しかしながら、陽極酸化
法によれば、数百Åの厚さでピンホールの無い絶
縁膜を得ることができ、耐圧も高い。半導体表面
に対する電界効果はゲートに印加する電圧を一定
すれば絶縁膜の誘電率に比例し厚さに反比例する
ので陽極酸化膜を用いることにより絶縁性を良好
に保持しながら厚さを薄くすることができ、極め
て大きな電界効果が期待される。 When using a TFT with the above structure, for example, for multiplex drive of a liquid crystal display device, the TFT
OFF resistance ( R OFF ) of
It requires a high off-ratio (R OFF /R ON ) and a high switching speed, and is also required to be stable for long-term operation. In order to realize a TFT that satisfies these characteristics,
The gate insulating film 3 of the TFT has (1) good insulation properties (no pinholes), high reliability and breakdown voltage, (2) low mobile ion density, and (3) interface state with the semiconductor. It is necessary to satisfy conditions such as low density and (4) large electric field effect on the semiconductor, but the above requirements (1) and (4) are contradictory and must be satisfied at the same time. It is difficult.
For example, SiO 2 can be removed by sputtering method, CVD method, etc.
When forming a thin film of Si 3 N 4 or the like, it is extremely difficult to form a thin film without pinholes if the thickness is less than 2000 to 3000 Å. However, according to the anodic oxidation method, an insulating film with a thickness of several hundred Å without pinholes can be obtained, and the withstand voltage is also high. The electric field effect on the semiconductor surface is proportional to the dielectric constant of the insulating film and inversely proportional to the thickness if the voltage applied to the gate is constant, so by using an anodic oxide film, the thickness can be reduced while maintaining good insulation properties. , and an extremely large electric field effect is expected.
一方、半導体層４としては、アモルフアスシリ
コンを単体として使用すると、従来用いられてき
たCdSe等の化合物半導体に於いて問題となる化
学量論的組成からのずれに起因する特性のばらつ
きが少なく、またエネルギーギヤツプも大きく真
性キヤリアの数が少ないこと等のTFT用半導体
層として優れた利点が得られる。しかしながらア
モルフアスシリコンに於いては、そのキヤリア移
動度が極めて小さく応答速度の点で問題があつ
た。一方、グロー放電により多量の水素で希釈し
たSiH4ガスを分解して形成したシリコン膜は微
結晶を含み、移動度が大であり、上記アモルフア
スシリコンのTFTとしての利点を損なうことな
く応答速度が改善される。従つて、陽極酸化膜を
ゲート絶縁膜３として組み合わせることにより、
極めて特性の良いTFTが作製されると考えられ
る。 On the other hand, when amorphous silicon is used alone as the semiconductor layer 4, there is less variation in properties due to deviations from the stoichiometric composition, which is a problem with conventionally used compound semiconductors such as CdSe. Furthermore, it has excellent advantages as a semiconductor layer for TFTs, such as a large energy gap and a small number of intrinsic carriers. However, amorphous silicon has extremely low carrier mobility and has a problem in terms of response speed. On the other hand, a silicon film formed by decomposing SiH 4 gas diluted with a large amount of hydrogen by glow discharge contains microcrystals, has high mobility, and has a high response speed without sacrificing the advantages of amorphous silicon as a TFT. is improved. Therefore, by combining the anodic oxide film as the gate insulating film 3,
It is thought that a TFT with extremely good characteristics will be produced.
しかしながら、陽極酸化膜にグロー放電よる微
結晶シリコン層を堆積するとグロー放電プロセス
における水素の存在によつてTa2O5が還元作用を
受け陽極酸化膜が損傷を受けて劣化し、絶縁性が
著しく低下するためTFTとゲート絶縁膜３とし
ての機能を果すことができなくなる。陽極酸化膜
をゲート絶縁膜３として用いる場合には必然的に
半導体層４の形成工程はゲート絶縁膜３の形成工
程の後でなければならず、このため上記絶縁性の
低下を回避することが良好なTFTを作製する上
で非常に重要な要件となる。 However, when a microcrystalline silicon layer is deposited on an anodic oxide film by glow discharge, Ta 2 O 5 is reduced due to the presence of hydrogen in the glow discharge process, damaging and deteriorating the anodic oxide film, resulting in a significant loss of insulation. As a result, the TFT and the gate insulating film 3 cannot function as each other. When an anodic oxide film is used as the gate insulating film 3, the process of forming the semiconductor layer 4 must necessarily be performed after the process of forming the gate insulating film 3, and therefore it is difficult to avoid the above-mentioned deterioration in insulation properties. This is a very important requirement in producing a good TFT.
＜発明の目的＞
本発明は上記問題点に鑑み、技術的手段を駆使
することにより、陽極酸化膜の絶縁低下を招くこ
となく微結晶シリコン層を半導体層として形成し
た新規有用なTFTの製造方法を提供することを
目的とするものである。<Purpose of the Invention> In view of the above problems, the present invention provides a new and useful method for manufacturing TFTs in which a microcrystalline silicon layer is formed as a semiconductor layer without deteriorating the insulation of the anodic oxide film by making full use of technical means. The purpose is to provide the following.
＜実施例＞
第２図は本発明の一実施例を説明するTFTの
構成断面図である。<Example> FIG. 2 is a sectional view of the configuration of a TFT explaining an example of the present invention.
ガラス基板１０上にTa膜を堆積した後、これ
を酒石酸アンモニウム水溶液に浸漬し、化成処理
する。65Vの定電圧化成で1000ÅのTa2O5膜が作
製され、この結果Taから成るゲート電極２０と
Ta表面の薄い酸化膜から成る第１の絶縁膜３０
が形成される。第１の絶縁膜３０上にはCVD法
又はスパツタリング法等で厚さ1000ÅのSi3N4膜
が第２の絶縁膜３１として積層される。第２の絶
縁膜３１は酸化を含有しない窒化膜であり、陽極
酸化されたTa2O5膜即ち第１の絶縁膜を保護する
機能を有する。この第１の絶縁膜３０と第２の絶
縁膜３１で２重ゲート絶縁層が構成される。次に
半導体層４０としてグロー放電により多量の水素
で希釈したSiH4ガス、例えばSiH4／（SiH4＋
H2）＝0.03を分解し、微結晶シリコン層を3000Å
積層し、次にソース電極５０及びドレイン電極６
０として3000ÅのTiを蒸着すると本実施例の
TFTが作製される。半導体層４０は微結晶シリ
コンの集合体あるいは一部が微結晶化したアモル
フアス（非晶質）シリコン層で構成される。また
微結晶シリコンの粒径は50Å程度から数百Å程度
に設定される。多量の水素で希釈したSiH4ガス
を用いてグロー放電すると得られる層はアモルフ
アスシリコン層中に微結晶シリコンが島状に点在
した状態となり、その粒径は一般的に50〜100Å
程度である。これを必要に応じて成長させると微
結晶シリコンが順次増加し、全体が多結晶体に移
行する。このTFTは保護膜７０としてCVD法に
よりSi3N4が3000Å積層され、半導体層４０がコ
ートされる。この保護膜７０は微結晶シリコン層
の保護のみならず半導体層４０の裏の表面（即ち
保護膜７０との界面）を空乏化し、オフ状態のリ
ーク電流を減少させ、TFTの特性を大きく向上
させる。 After a Ta film is deposited on the glass substrate 10, it is immersed in an ammonium tartrate aqueous solution and subjected to chemical conversion treatment. A Ta 2 O 5 film with a thickness of 1000 Å was fabricated by constant voltage formation at 65 V, and as a result, a gate electrode 20 made of Ta was formed.
First insulating film 30 made of a thin oxide film on the Ta surface
is formed. A Si 3 N 4 film having a thickness of 1000 Å is laminated as a second insulating film 31 on the first insulating film 30 by a CVD method, a sputtering method, or the like. The second insulating film 31 is a nitride film that does not contain oxidation, and has the function of protecting the anodized Ta 2 O 5 film, that is, the first insulating film. The first insulating film 30 and the second insulating film 31 constitute a double gate insulating layer. Next, as the semiconductor layer 40, SiH 4 gas diluted with a large amount of hydrogen by glow discharge, for example, SiH 4 /(SiH 4 +
H 2 ) = 0.03 and the microcrystalline silicon layer is 3000Å
Then, the source electrode 50 and the drain electrode 6 are stacked.
In this example, if 3000 Å of Ti is deposited as 0,
TFT is fabricated. The semiconductor layer 40 is composed of an aggregate of microcrystalline silicon or a partially microcrystalline amorphous silicon layer. Further, the grain size of the microcrystalline silicon is set to about 50 Å to several hundred Å. The layer obtained by glow discharge using SiH 4 gas diluted with a large amount of hydrogen is an amorphous silicon layer with microcrystalline silicon scattered in the form of islands, and the grain size is generally 50 to 100 Å.
That's about it. When this is grown as necessary, microcrystalline silicon gradually increases, and the whole becomes polycrystalline. This TFT is coated with a semiconductor layer 40 by stacking Si 3 N 4 to a thickness of 3000 Å as a protective film 70 by the CVD method. This protective film 70 not only protects the microcrystalline silicon layer, but also depletes the back surface of the semiconductor layer 40 (i.e., the interface with the protective film 70), reduces leakage current in the off state, and greatly improves the characteristics of the TFT. .
上記実施例に於いて、Si3N4の比誘電率を6.4、
Ta2O5の比誘電率を26.0とすれば、ゲート絶縁膜
をSi3N4のみで形成して本実施例と同等の電界効
果を得るには1250Å程度の厚さに層設することが
必要であるが、これではピンホールのために絶縁
特性が劣化する。しかるに上記実施例の如くゲー
ト絶縁膜をTa2O5膜とSi3O4膜の複合膜で構成し
た場合、Ta2O5膜にはピンホール等の発生がなく
高い絶縁特性が得られる。またTa2O5膜上に
Si3N4膜を堆積することにより、微結晶シリコン
層をグロー放電で形成する際にSi3N4膜がTa2O5
膜を保護することとなりTa2O5膜の酸素原子が離
脱することがなく、従つて半導体層４形成後も絶
縁性の良好なTa2O5膜を維持することができる。 In the above example, the dielectric constant of Si 3 N 4 is 6.4,
If the dielectric constant of Ta 2 O 5 is 26.0, in order to form the gate insulating film only with Si 3 N 4 and obtain the same electric field effect as in this example, it is necessary to form a layer with a thickness of about 1250 Å. Although necessary, this degrades the insulation properties due to pinholes. However, when the gate insulating film is composed of a composite film of a Ta 2 O 5 film and a Si 3 O 4 film as in the above embodiment, the Ta 2 O 5 film is free from pinholes and has high insulating properties. Also on Ta 2 O 5 film
By depositing the Si 3 N 4 film, the Si 3 N 4 film becomes Ta 2 O 5 when forming the microcrystalline silicon layer by glow discharge.
Since the film is protected, the oxygen atoms of the Ta 2 O 5 film are not released, and therefore the Ta 2 O 5 film with good insulation properties can be maintained even after the semiconductor layer 4 is formed.
ゲート電極２０はTaで構成されているが、ｎ
チヤんネル動作のTFTに於いては、Al等の場合
と比較してTaの仕事関数が大きいのでピンチオ
フ電圧が正となり、ノーマル・オフのTFTが得
られ、ゲート電圧がOVでの抵抗（オフ抵抗）が
高くなり、液晶マトリツクス駆動用TFTとして
適する特性が得られる。また保護膜７０は、
TFTの半導体層が直接大気と接触することを防
止し、微結晶シリコン層のゲートと逆の面（裏
面）に於けるバンドの曲がりを少なくし、特性の
安定化を向上せしめると同時にオフ抵抗を高く保
持する作用を有する。更に液晶表示素子を駆動す
るための一方のセル基板に適用した場合にも液晶
層とTFTが直接接触するのを防止し、TFTの寿
命特性の向上に寄与する。その他上記保護膜７０
は、光の遮蔽のため金属層をTFTの活性領域上
に形成する場合にも重要で、保護膜７０上に金属
層を設け、TFTの活性領域を蔽つた場合にもリ
ークによりオフ抵抗が低下するといつた問題がな
い。このように半導体層４０は安定な２重ゲート
絶縁膜上に堆積されるため、この界面でリーク等
を生ずることがなくまた他方の界面には絶縁保護
膜７０が被覆されてオフ時のリーク電流を減少さ
せる作用が働くため、TFTとしての動作特性を
非常に信頼性あるものとすることができる。 The gate electrode 20 is made of Ta, but n
In channel-operated TFTs, the work function of Ta is larger than that of Al, etc., so the pinch-off voltage is positive, resulting in a normally-off TFT, and the resistance (off-off) when the gate voltage is OV. This increases the resistance (resistance) and provides characteristics suitable for use as a TFT for driving liquid crystal matrices. Further, the protective film 70 is
It prevents the TFT semiconductor layer from coming into direct contact with the atmosphere, reduces band bending on the surface opposite to the gate (back surface) of the microcrystalline silicon layer, improves the stability of characteristics, and at the same time reduces off-resistance. It has the effect of holding it high. Furthermore, when applied to one cell substrate for driving a liquid crystal display element, it prevents direct contact between the liquid crystal layer and the TFT, contributing to improving the life characteristics of the TFT. Other above protective film 70
This is also important when a metal layer is formed on the active region of the TFT to shield light. Even when a metal layer is provided on the protective film 70 to cover the active region of the TFT, the off-resistance decreases due to leakage. Then there are no problems. Since the semiconductor layer 40 is deposited on the stable double gate insulating film in this way, no leakage occurs at this interface, and the other interface is covered with the insulating protective film 70 to prevent leakage current during off-time. Since it has the effect of reducing
第３図は上述のTFTに於けるドレイン電流−
ゲート電圧特性（VDS＝＋10V）を示すものであ
る。測定したTFTはソース電極５０とドレイン
電極６０間の間隔に対応するチヤネル長Ｌが40μ
ｍ、チヤネル幅Ｗが2000μｍのものである。また
ソースドレイン間の電圧VDSは10Vである。ゲー
ト電圧が0V〜＋5Vの範囲において３桁以上、0V
〜＋10Vの範囲において５桁のオン・オフ比（ド
レイン電流比）が得られていることがわかる。 Figure 3 shows the drain current in the TFT mentioned above.
This shows the gate voltage characteristics (V DS = +10V). The measured TFT has a channel length L of 40μ, which corresponds to the distance between the source electrode 50 and the drain electrode 60.
m, and the channel width W is 2000 μm. Further, the source-drain voltage V DS is 10V. 3 digits or more in the gate voltage range of 0V to +5V, 0V
It can be seen that a five-digit on-off ratio (drain current ratio) is obtained in the range of ~+10V.
以上詳説した如く、本発明はゲート絶縁膜を陽
極酸化膜とこの陽極酸化膜を微結晶シリコンのグ
ロー放電形成時に保護する保護膜との複合絶縁膜
で形成するとともにこの上に堆積される微結晶シ
リコン半導体の他方の界面にはソース・ドレイン
電極及びソース・ドレイン電極で被覆されない露
呈部分に絶縁保護膜を被着形成することにより信
頼性の高いかつ特性の良好な微結晶シリコンの
TFTを構成する製造技術であり、その技術的意
義は多大である。 As explained in detail above, the present invention forms a gate insulating film with a composite insulating film consisting of an anodic oxide film and a protective film that protects this anodic oxide film during the formation of a glow discharge of microcrystalline silicon, and the microcrystals deposited thereon. On the other interface of the silicon semiconductor, an insulating protective film is formed on the source/drain electrodes and the exposed portions not covered by the source/drain electrodes, thereby creating microcrystalline silicon with high reliability and good characteristics.
This is a manufacturing technology that makes up TFTs, and its technological significance is enormous.
第１図は従来のTFTの基本的構成を示す断面
図である。第２図は本発明の一実施例を示す
TFTの基本的構成図である。第３図は第２図に
示すTFTのドレイン電流対ゲート電圧特性を示
す説明図である。
１０……ガラス基板、２０……ゲート電極、３
０……第１の絶縁膜、３１……第２の絶縁膜、４
０……半導体層、５０……ソース電極、６０……
ドレイン電極、７０……保護膜。
FIG. 1 is a sectional view showing the basic structure of a conventional TFT. FIG. 2 shows an embodiment of the present invention.
It is a basic configuration diagram of TFT. FIG. 3 is an explanatory diagram showing the drain current versus gate voltage characteristics of the TFT shown in FIG. 2. 10...Glass substrate, 20...Gate electrode, 3
0...First insulating film, 31... Second insulating film, 4
0... Semiconductor layer, 50... Source electrode, 60...
Drain electrode, 70...protective film.
Claims (1)
後、該Ta膜表面を陽極酸化してTa2O5から成る
第１のゲート絶縁膜を形成する工程と、該第１の
ゲート絶縁膜上に窒化膜から成る第２のゲート絶
縁膜を被覆した後、該第２のゲート絶縁膜を下地
層として微結晶シリコンを主とする半導体層をグ
ロー放電法で積層する工程と、該半導体層にソー
ス電極及びドレイン電極を配置する工程と、を具
備して成ることを特徴とする薄膜トランジスタの
製造方法。1. After depositing a Ta film to serve as a gate electrode on a substrate, the surface of the Ta film is anodized to form a first gate insulating film made of Ta 2 O 5 ; After coating the second gate insulating film made of a nitride film, a step of laminating a semiconductor layer mainly made of microcrystalline silicon using the second gate insulating film as a base layer by a glow discharge method; 1. A method of manufacturing a thin film transistor, comprising the step of arranging a source electrode and a drain electrode.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58015748A JPS59141271A (en) | 1983-01-31 | 1983-01-31 | Thin-film transistor |
| GB08305371A GB2118774B (en) | 1982-02-25 | 1983-02-25 | Insulated gate thin film transistor |
| AU31862/84A AU549564B2 (en) | 1983-01-31 | 1984-08-13 | Photo electric transducer |
| AU33519/84A AU568148B2 (en) | 1983-01-31 | 1984-09-26 | Woven slide fastener |
| US07/968,453 US5340999A (en) | 1982-02-25 | 1992-10-29 | Insulated gate thin film transistor with amorphous or microcrystalline semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58015748A JPS59141271A (en) | 1983-01-31 | 1983-01-31 | Thin-film transistor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21056092A Division JPH0691256B2 (en) | 1992-08-07 | 1992-08-07 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59141271A JPS59141271A (en) | 1984-08-13 |
| JPH0582069B2 true JPH0582069B2 (en) | 1993-11-17 |
Family
ID=11897382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58015748A Granted JPS59141271A (en) | 1982-02-25 | 1983-01-31 | Thin-film transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS59141271A (en) |
| AU (2) | AU549564B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214476A (en) * | 1985-03-19 | 1986-09-24 | Agency Of Ind Science & Technol | Thin-film transistor |
| JPS62156375A (en) * | 1985-12-27 | 1987-07-11 | 小牧 貢 | Cloth having resist style pattern |
| JPH0691258B2 (en) * | 1986-03-31 | 1994-11-14 | セイコー電子工業株式会社 | Thin film transistor |
| JPS63265286A (en) * | 1987-04-23 | 1988-11-01 | セイコーエプソン株式会社 | Active matrix liquid crystal panel |
| JPH061314B2 (en) * | 1987-07-30 | 1994-01-05 | シャープ株式会社 | Thin film transistor array |
| JP2613403B2 (en) * | 1987-11-13 | 1997-05-28 | 日本電信電話株式会社 | Method for manufacturing thin film transistor |
| JPH01231025A (en) * | 1988-03-11 | 1989-09-14 | Seikosha Co Ltd | Thin-film transistor array |
| US5210050A (en) | 1990-10-15 | 1993-05-11 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device comprising a semiconductor film |
| JP2594384B2 (en) * | 1990-11-16 | 1997-03-26 | 松下電器産業株式会社 | Metal oxide thin film, method of manufacturing the same, and electronic device using the metal oxide thin film |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| EP0499979A3 (en) | 1991-02-16 | 1993-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| JPH0595002A (en) * | 1991-10-02 | 1993-04-16 | Sharp Corp | Thin-film transistor |
| JPH05129608A (en) * | 1991-10-31 | 1993-05-25 | Sharp Corp | Semiconductor device |
| US5796116A (en) * | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
| AUPN679295A0 (en) * | 1995-11-23 | 1995-12-14 | Unisearch Limited | Conformal films for light-trapping in thin silicon solar cells |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669864A (en) * | 1979-11-09 | 1981-06-11 | Japan Electronic Ind Dev Assoc<Jeida> | Thin-film transistor |
| JPS57153427A (en) * | 1981-03-17 | 1982-09-22 | Fujitsu Ltd | Manufacture of thin film device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DK129376B (en) * | 1969-03-21 | 1974-10-07 | Italo Americana Prentice Spa | Zipper half with a fastening element in the form of a continuous screw winding and with a zipper strap woven with the screw winding. |
-
1983
- 1983-01-31 JP JP58015748A patent/JPS59141271A/en active Granted
-
1984
- 1984-08-13 AU AU31862/84A patent/AU549564B2/en not_active Ceased
- 1984-09-26 AU AU33519/84A patent/AU568148B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669864A (en) * | 1979-11-09 | 1981-06-11 | Japan Electronic Ind Dev Assoc<Jeida> | Thin-film transistor |
| JPS57153427A (en) * | 1981-03-17 | 1982-09-22 | Fujitsu Ltd | Manufacture of thin film device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59141271A (en) | 1984-08-13 |
| AU568148B2 (en) | 1987-12-17 |
| AU3186284A (en) | 1985-03-21 |
| AU3351984A (en) | 1985-04-18 |
| AU549564B2 (en) | 1986-01-30 |
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