KR100449248B1 - Method for forming capacitor using the Atomic Layer Deposition - Google Patents
Method for forming capacitor using the Atomic Layer Deposition Download PDFInfo
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- KR100449248B1 KR100449248B1 KR10-2001-0085363A KR20010085363A KR100449248B1 KR 100449248 B1 KR100449248 B1 KR 100449248B1 KR 20010085363 A KR20010085363 A KR 20010085363A KR 100449248 B1 KR100449248 B1 KR 100449248B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
본 발명은 커패시터 유전전층을 산화 저항성 높고 표면 거칠기가 작은 ALD(Atomic Layer Deposition) 질화막(SiOxNy)를 사용하여 소자의 신뢰성을 높인 원자층 증착을 이용한 커패시터 형성 방법에 관한 것으로, 반도체 기판상에 스토리지 전극을 형성하는 단계;상기 스토리지 전극 표면에 ALD Si3N4(SiOxNy) 박막을 증착하는 공정과, 상기 Si3N4박막의 표면을 산화시키는 공정으로 유전체층을 형성하는 단계;상기 유전체층상에 플레이트 전극을 형성하는 단계를 포함하여 구성된다.The present invention relates to a method for forming a capacitor using atomic layer deposition, in which the reliability of the device is improved by using an atomic layer deposition (ALD) nitride film (SiOxNy) having high oxidation resistance and low surface roughness. Forming a dielectric layer by depositing an ALD Si 3 N 4 (SiOxNy) thin film on the surface of the storage electrode and oxidizing the surface of the Si 3 N 4 thin film; a plate electrode on the dielectric layer It comprises a step of forming.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 커패시터 유전전층을 산화 저항성 높고 표면 거칠기가 작은 ALD(Atomic Layer Deposition) 질화막(SiOxNy)를 사용하여 소자의 신뢰성을 높인 원자층 증착을 이용한 커패시터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of forming a capacitor using atomic layer deposition in which a capacitor dielectric layer has high oxidation resistance and small surface roughness using ALD (Atomic Layer Deposition) nitride film (SiOxNy). It is about.
일반적으로 박막(thin film)은 반도체 소자의 유전체(dielectrics), 액정표시소자(liquid-crystal display)의 투명한 도전체(transparant conductor) 및 전자 발광 박막 표시 소자(electroluminescent thin film display)의 보호층(protective layer) 등으로 다양하게 사용된다.In general, a thin film is a protective layer of a dielectric of a semiconductor device, a transparent conductor of a liquid-crystal display, and an electroluminescent thin film display. layer) and so on.
이와 같은 박막을 형성하기 위한 ALD법은 반응물을 순차적으로 주입하고 제거하는 방식으로 막을 증착시키는 방법이다.The ALD method for forming such a thin film is a method of depositing a film by sequentially injecting and removing reactants.
이러한 ALD법은 하부막질의 특성에 따라 형성되는 박막의 성질이 좌우되는 에피공정의 특성을 갖고 있어 ALE(Atomic layer epitaxy)라고도한다.This ALD method is also called ALE (Atomic layer epitaxy) because it has an epitaxial process in which the properties of the thin film formed depending on the characteristics of the lower film quality.
그러므로 ALD 방법에 의해 증착되는 박막은 하부 막질이 단결정일 경우 단결정의 막이 증착되고, 하부 막질이 비정질일 경우 비정질의 막이 증착되게 된다.Therefore, in the thin film deposited by the ALD method, a single crystal film is deposited when the lower film quality is a single crystal, and an amorphous film is deposited when the lower film quality is amorphous.
이하에서 종래 기술의 반도체 소자의 커패시터 형성 공정에 관하여 설명한다.Hereinafter, a capacitor forming process of the semiconductor device of the prior art will be described.
도 1은 종래 기술의 질화막을 이용한 커패시터의 스토리지 노드의 산화 현상을 나타낸 단면 사진이고, 도 2는 LPCVD 공정에 의한 질화막의 증착 온도에 따른 산화저항성 변화 그래프이다.1 is a cross-sectional view showing the oxidation phenomenon of the storage node of the capacitor using a nitride film of the prior art, Figure 2 is a graph of the oxidation resistance change according to the deposition temperature of the nitride film by the LPCVD process.
종래 기술의 NO(Si3N4/SiO2) 커패시터는 여러 가지 요소가 구비된 웨이퍼에 다양한 형상으로 스토리지 노드를 형성한 후 HF 용액으로 스토리지 노드 표면의 산화막을 제거(전세정공정)한다.Conventional NO (Si 3 N 4 / SiO 2 ) capacitors form a storage node in various shapes on a wafer having various elements, and then remove an oxide film on the surface of the storage node with a HF solution (pre-cleaning process).
LPCVD(Low Pressure Chemical Vapor Deposition) Si3N4박막을 증착한 후 산화막 공정을 진행한후에 플레이트 전극을 형성한다.A low pressure chemical vapor deposition (LPCVD) Si 3 N 4 thin film is deposited and then plate electrodes are formed after an oxide film process is performed.
디자인 룰의 감소로 셀 면적 또한 감소하기 때문에 필요한 충전 용량을 얻으려면 유전체의 유효 두께(Teff)를 감소시켜야 한다.Reducing design rules also reduces cell area, so the effective thickness (Teff) of the dielectric must be reduced to achieve the required charge capacity.
종래 기술의 NO 유전체는 도 1에서와 같이, LPCVD Si3N4의 산화 저항성이 40Å이하의 두께에서 급속히 감소하기 때문에 후속 공정시에 스토리지 노드 및 비트 라인과 같은 커패시터 하부의 구성 요소가 산화되는 문제가 있다.In the prior art NO dielectric, as shown in Fig. 1, the oxidation resistance of LPCVD Si 3 N 4 rapidly decreases in a thickness of 40 kΩ or less, so that components under the capacitor such as storage nodes and bit lines are oxidized in a subsequent process. There is.
그러나 LPCVD Si3N4의 경우에는 50Å 이하의 두께에서는 누설 전류증가 및 절연파괴전압 감소로 Teff를 45Å 이하로 낮추는데 어려움이 있다.However, in the case of LPCVD Si 3 N 4 , it is difficult to reduce the Teff to 45 mA or less due to an increase in leakage current and a decrease in dielectric breakdown voltage at a thickness of 50 mA or less.
그러나 이와 같은 종래 기술의 반도체 소자의 커패시터의 형성 공정에 있어서는 다음과 같은 문제가 있다.However, in the process of forming the capacitor of the semiconductor device of the prior art, there are the following problems.
Si3N4증착 공정의 온도가 낮으면 도 2에서와 같이, 산화저항성이 증가한다.When the temperature of the Si 3 N 4 deposition process is low, as shown in FIG. 2, oxidation resistance is increased.
Si3N4의 산화저항성이 증가하면 유전체의 두께를 낮출 수 있으나, 종래 기술에서는 산화 저항성을 유지하면서 두께를 낮추는 것이 어렵다.Increasing the oxidation resistance of Si 3 N 4 can lower the thickness of the dielectric, but in the prior art it is difficult to reduce the thickness while maintaining the oxidation resistance.
본 발명은 이와 같은 종래 기술의 커패시터 유전체 형성 공정의 문제를 해결하기 위한 것으로, 커패시터 유전전층을 산화 저항성 높고 표면 거칠기가 작은 ALD(Atomic Layer Deposition) 질화막(SiOxNy)를 사용하여 소자의 신뢰성을 높인원자층 증착을 이용한 커패시터 형성 방법을 제공하기 위한 것이다.The present invention is to solve such a problem of the conventional capacitor dielectric formation process, the atomic resistance layer of the capacitor using a high oxidation resistance and small surface roughness ALD (Atomic Layer Deposition) nitride film (SiOxNy) to increase the reliability of the device It is to provide a method for forming a capacitor using layer deposition.
도 1은 종래 기술의 질화막을 이용한 커패시터의 스토리지 노드의 산화 현상을 나타낸 단면 사진1 is a cross-sectional view showing the oxidation phenomenon of the storage node of the capacitor using a nitride film of the prior art
도 2는 LPCVD 공정에 의한 질화막의 증착 온도에 따른 산화저항성 변화 그래프2 is a graph of oxidation resistance change according to the deposition temperature of a nitride film by LPCVD process
도 3a내지 도 3c는 본 발명에 따른 ALD 공정에 의한 유전체막의 표면 거칠기를 비교한 사진3a to 3c are photographs comparing the surface roughness of the dielectric film by the ALD process according to the present invention
이와 같은 목적을 달성하기 위한 본 발명에 따른 원자층 증착을 이용한 커패시터 형성 방법은 반도체 기판상에 스토리지 전극을 형성하는 단계;상기 스토리지 전극 표면에 ALD Si3N4(SiOxNy) 박막을 증착하는 공정과, 상기 Si3N4박막의 표면을 산화시키는 공정으로 유전체층을 형성하는 단계;상기 유전체층상에 플레이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a capacitor using atomic layer deposition, the method comprising: forming a storage electrode on a semiconductor substrate; depositing an ALD Si 3 N 4 (SiOxNy) thin film on the storage electrode surface; Forming a dielectric layer by oxidizing a surface of the Si 3 N 4 thin film; forming a plate electrode on the dielectric layer.
이하에서 본 발명에 따른 원자층 증착을 이용한 커패시터 형성 방법에 관하여 상세히 설명한다.Hereinafter, a method of forming a capacitor using atomic layer deposition according to the present invention will be described in detail.
도 3a내지 도 3c는 본 발명에 따른 ALD 공정에 의한 유전체막의 표면 거칠기를 비교한 사진이다.3a to 3c are photographs comparing the surface roughness of the dielectric film by the ALD process according to the present invention.
도 3a는 SiO2를 나타낸 것으로, 표면 거칠기가 0.030㎚,도 3b는 ALD SiN/SiO2박막의 표면을 나타낸 것으로 표면 거칠기가 0.031㎚, 도 3c는 LPCVD SiN/SiO2박막을 나타낸 것으로 표면 거칠기가 0.043㎚이다.3A shows SiO 2 , the surface roughness is 0.030 nm, and FIG. 3B shows the surface of the ALD SiN / SiO 2 thin film, the surface roughness is 0.031 nm, and FIG. 3C shows the LPCVD SiN / SiO 2 thin film. 0.043 nm.
본 발명은 LPCVD Si3N4보다 산화 저항성이 높고 표면 거칠기가 작은 ALD Si3N4(SiOxNy)을 유전체로 사용하여 Teff을 낮추고 누설전류 특성을 개선하는 것이다.The present invention uses ALD Si 3 N 4 (SiOxNy), which has higher oxidation resistance and lower surface roughness than LPCVD Si 3 N 4 , to lower Teff and improve leakage current characteristics.
ALD Si3N4(SiOxNy)는 공정 온도가 250℃ ~ 500℃로 LPCVD 공정 온도인 600℃ ~ 800℃보다 300℃정도 낮기 때문에 고온 열공정에 의한 트랜지스터 및 접합 특성의 열화를 막을 수 있고 산화 저항성이 큰 Si3N4박막을 증착할 수 있어 유전체의 두께를 낮출 수 있다.Since ALD Si 3 N 4 (SiOxNy) has a process temperature of 250 ° C to 500 ° C and 300 ° C below the LPCVD process temperature of 600 ° C to 800 ° C, it is possible to prevent deterioration of transistor and junction characteristics due to high temperature thermal process and to resist oxidation This large Si 3 N 4 thin film can be deposited to lower the thickness of the dielectric.
유전체의 두께가 얇아질수록 유전체 박막의 표면 거칠기(surface roughness)는 전기적 특성에 큰 영향을 미친다.As the thickness of the dielectric becomes thinner, the surface roughness of the dielectric thin film greatly affects the electrical properties.
즉, 커패시터 양단에 인가되는 전압은 일정하므로 유전체의 두께가 감소하면 전계(electrical field)가 증가하게 되고 표면이 거친 곳에는 부분적인 전계 집중(local electrical field concentration)이 더욱 심하게 발생하고 다른 거친 표면상태는 계면에 많은 점결함(point defect)을 발생시켜 전자나 정공의 트랩 사이트(trap site)로 작용하기 때문에 전기적 특성이 열화된다.In other words, the voltage applied across the capacitor is constant, so as the thickness of the dielectric decreases, the electric field increases, and when the surface is rough, local electrical field concentration occurs more severely, and other rough surface conditions occur. Because of the many point defects at the interface acts as a trap site of electrons or holes deteriorates the electrical properties.
ALD Si3N4(SiOxNy)는 CVD Si3N4에 비하여 저온 공정의 이점이 있고 표면 거칠기가 작아서 두께를 낮추어도 전기적 특성이 CVD에 비해 우수하다.ALD Si 3 N 4 (SiOxNy) has the advantages of low temperature process compared to CVD Si 3 N 4 , and its electrical properties are superior to CVD even at low thickness due to its small surface roughness.
본 발명의 공정 진행은 스토리지 전극을 형성하는 단계, ALD Si3N4(SiOxNy) 박막을 증착하는 단계, Si3N4박막의 표면을 산화시키는 단계, 폴리 실리콘을 증착하여 플레이트 전극을 형성하는 단계로 구성된다.The process of the present invention comprises the steps of forming a storage electrode, depositing an ALD Si 3 N 4 (SiOxNy) thin film, oxidizing the surface of the Si 3 N 4 thin film, depositing polysilicon to form a plate electrode It consists of.
스토리지 전극은 P 농도를 극대화하면서 MPS(Meta Stable Polysilicon)에 의한 면적 증가를 위해 2층 이상의 다층으로 증착한다.Storage electrodes are deposited in two or more layers to maximize the P concentration while increasing the area by the Meta Stable Polysilicon (MPS).
유전체는 ALD 방법으로 Si3N4혹은 SiOxNy를 증착한다. 이때 Si 소오스로는 SiH4, SiH2Cl2, SiCl4등의 가스를 사용하고, N 소오스로는 NH3, N2등의 가스를 사용한다.The dielectric is deposited Si 3 N 4 or SiO x N y by the ALD method. At this time, gases such as SiH 4 , SiH 2 Cl 2 , and SiCl 4 are used as the Si source, and gases such as NH 3 and N 2 are used as the N source.
그리고 O의 소오스로는 O2, O3, H2O 등의 가스를 사용하여 "Si pulse → purge → N pulse → purge"를 1 사이클로 Si3N4를 증착하거나 "Si pulse → purge → N pulse → purge → O pulse → purge"를 1 사이클로 SiOxNy를 증착한다.In addition, as a source of O, Si 3 N 4 is deposited in one cycle using "Si pulse → purge → N pulse → purge" using gas such as O 2 , O 3 , H 2 O or "Si pulse → purge → N pulse". → purge → O pulse → purge ”to deposit SiOxNy in 1 cycle.
ALD Si3N4를 증착한 후 표면을 산화시켜 절연 특성을 높인다.After depositing ALD Si 3 N 4 , the surface is oxidized to improve insulation properties.
그리고 플레이트 전극은 비정질로 증착하여 P를 고용 한계보다 높게 도핑하거나, 증착 압력을 높여 P 농도를 높이거나, P를 이온 주입하여 P 농도를 높인다.The plate electrode is amorphous deposited to dope P higher than the solid solution limit, the deposition pressure is increased to increase the P concentration, or P is ion-implanted to increase the P concentration.
플레이트 전극을 형성하기 위한 실리콘을 증착시키기 위하여 불순물 농도를 높이는 공정을 사용하고, 베이스 가스로 DCS(Si2H6) 또는 MS(SiH4) 가스를 사용한다.In order to deposit the silicon for forming the plate electrode, a process of increasing the impurity concentration is used, and DCS (Si 2 H 6 ) or MS (SiH 4 ) gas is used as the base gas.
그리고 불순물 원료 가스로는 1~5% PH3/H2또는 PH3/SiH4가스를 사용한다.In addition, 1 to 5% PH 3 / H 2 or PH 3 / SiH 4 gas is used as the impurity raw material gas.
여기서의 공정 압력은 2torr 이하로 하고, 증착 온도는 500℃~570℃로 실리콘이 비정질 상태로 증착되도록 한다.The process pressure here is 2torr or less and the deposition temperature is 500 ℃ ~ 570 ℃ to allow the silicon to be deposited in an amorphous state.
이때 사용 가스의 양은 base 가스 800~2000㎖(cc), 불순물 가스는 150~500㎖(cc)사용하고 두께는 100~1000Å 정도로 한다.At this time, the amount of gas used is 800 ~ 2000mL (cc) base gas, 150 ~ 500mL (cc) impurity gas is used and the thickness is about 100 ~ 1000Å.
본 발명은 커패시터 외에도 고집적 디바이스의 게이트 유전막 형성에 사용할수 있다.The present invention can be used to form gate dielectric films of highly integrated devices in addition to capacitors.
이와 같은 본 발명에 따른 원자층 증착을 이용한 커패시터 형성 방법은 다음과 같은 효과가 있다.Such a capacitor formation method using atomic layer deposition according to the present invention has the following effects.
본 발명은 저온 공정과 낮은 표면 거칠기로 인하여 유전체의 두께를 감소시켜 Teff을 40Å이하로 낮출 수 있어서 NO 커패시터의 충전용량을 극대화할 수 있다.The present invention can reduce the thickness of the dielectric due to the low temperature process and low surface roughness, thereby lowering the Teff to 40 kΩ or less, thereby maximizing the charging capacity of the NO capacitor.
또한, 높은 충전 용량으로 인하여 커패시터의 높이를 낮출 수 있어 전후 공정이 용이해지는 효과가 있고 결함 발생 빈도를 감소시킬 수 있다.In addition, due to the high charging capacity, the height of the capacitor can be lowered, thereby facilitating the front and rear process and reducing the frequency of defect occurrence.
높은 충전용량과 적은 결함 발생으로 인하여 소자의 신뢰성, 리프레쉬 특성을 개선시킬 수 있다.High charge capacity and fewer defects can improve device reliability and refresh characteristics.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4289797A (en) * | 1979-10-11 | 1981-09-15 | Western Electric Co., Incorporated | Method of depositing uniform films of Six Ny or Six Oy in a plasma reactor |
| KR20000008014A (en) * | 1998-07-09 | 2000-02-07 | 윤종용 | Capacitor of semiconductor devices and method thereof |
| KR20010110527A (en) * | 2000-06-07 | 2001-12-13 | 윤종용 | Metal-insulator-metal capacitor and manufacturing method thereof |
| KR20020096798A (en) * | 2001-06-20 | 2002-12-31 | 삼성전자 주식회사 | A method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4289797A (en) * | 1979-10-11 | 1981-09-15 | Western Electric Co., Incorporated | Method of depositing uniform films of Six Ny or Six Oy in a plasma reactor |
| KR20000008014A (en) * | 1998-07-09 | 2000-02-07 | 윤종용 | Capacitor of semiconductor devices and method thereof |
| KR20010110527A (en) * | 2000-06-07 | 2001-12-13 | 윤종용 | Metal-insulator-metal capacitor and manufacturing method thereof |
| KR20020096798A (en) * | 2001-06-20 | 2002-12-31 | 삼성전자 주식회사 | A method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane |
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