JPH01114080A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH01114080A JPH01114080A JP27014187A JP27014187A JPH01114080A JP H01114080 A JPH01114080 A JP H01114080A JP 27014187 A JP27014187 A JP 27014187A JP 27014187 A JP27014187 A JP 27014187A JP H01114080 A JPH01114080 A JP H01114080A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- thickness
- built
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 150000003376 silicon Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 101100042630 Caenorhabditis elegans sin-3 gene Proteins 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 230000007774 longterm Effects 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜トランジスタ（Ｔ Ｐ Ｔ）に係り。[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film transistor (TPT).
特に、窒化シリコン（Ｓ ｉ Ｎ）をゲート絶縁膜とし
、非晶質水素化シリコン（ａ−５ｉ）を半導体膜とする
ＴＰＴの閾値電圧のシフトを低減するに好適なトランジ
スタ構造に関する。In particular, the present invention relates to a transistor structure suitable for reducing the threshold voltage shift of a TPT in which silicon nitride (S i N) is used as a gate insulating film and amorphous silicon hydride (a-5i) is used as a semiconductor film.
従来のａ−８ｉを半導体膜とするＴＰＴは、特開昭５８
−３２８９号に記載のように、ゲート絶縁膜にＳｉＮと
ａ−８ｉを連続してｐ−ｃｖｐ法で堆積する方法がとら
れていた。この方法は、ＳｉＮとａ−８ｉ界面の準位の
低減に有効であり、そのため、ＴＰＴの動作安定性もこ
の方式で作られたものが最良であると信じられていた。The conventional TPT using a-8i as a semiconductor film was disclosed in Japanese Patent Application Laid-open No. 1983.
As described in No. 3289, a method was used in which SiN and a-8i were successively deposited on the gate insulating film by the p-cvp method. This method is effective in reducing the level at the interface between SiN and a-8i, and it was therefore believed that the operational stability of the TPT made using this method is the best.
しかしながら、従来技術で作製されたＴＰＴにゲート電
圧を印加して長時間放置した場合、閾値電圧がしだいに
シフトするという問題は残されたま゛まであった。この
シフト量は、ＳｉＮ及びａ −８ｉ膜堆積温度の上昇に
より減少するなど膜製作条性を改良することにより低減
は出来るが、まだ、充分な値ではなかった。However, the problem remains that when a gate voltage is applied to a TPT manufactured by the conventional technique and left for a long time, the threshold voltage gradually shifts. Although this shift amount can be reduced by improving the film fabrication properties, such as by increasing the SiN and a-8i film deposition temperature, it is still not a sufficient value.
上記した閾値電圧のシフトは、ＳｉＮゲート絶縁膜の半
導体層（ａ−８ｉ層）側表面に極めて薄い酸化層を形成
することにより、大幅に低減できる。The above threshold voltage shift can be significantly reduced by forming an extremely thin oxide layer on the semiconductor layer (a-8i layer) side surface of the SiN gate insulating film.
ＳｉＮ表面に酸化層を形成した場合とＳｉＮを酸化物１
例えば５ｉｆｔに変えた場合とでは闇値電圧のシフトの
状況はまったく異なり、その改善の原理は不明である。When an oxide layer is formed on the SiN surface and when SiN is formed as an oxide 1
For example, when changing to 5ift, the shift of the dark value voltage is completely different, and the principle behind the improvement is unknown.
以下１本発明の一実施例を第１図により説明する。まず
、ガラス基板１上にＣｒ膜２を堆積した後、ホトエツチ
ング法により、ゲート電極パターンに加工する。その後
、プラズマＣＶＤ法でＳｉＮ３を堆積した。この堆積に
はＳｉＨ４とＮＨａ 、Ｎｘ混合ガスを使用した。Ｓｉ
Ｎ膜の厚さは０．３ μｍである。その後、同−ＣＶＤ
装置中に０２ガスを導入した。ガス圧力は０．０６Ｔ
ｏ ｒ ｒである。高周波電力を０．０２ Ｗ／ｌ−ｊ
の密度で印加することにより酸素プラズマ、を形成し、
ＳｉＮ表面を酸化して酸化層４を形成した。放電時間は
２０分であり、基板温度は３２０℃である。An embodiment of the present invention will be described below with reference to FIG. First, a Cr film 2 is deposited on a glass substrate 1, and then processed into a gate electrode pattern by photoetching. Thereafter, SiN3 was deposited by plasma CVD. A mixed gas of SiH4, NHa, and Nx was used for this deposition. Si
The thickness of the N film is 0.3 μm. After that, the same-CVD
02 gas was introduced into the apparatus. Gas pressure is 0.06T
It's o r r. High frequency power 0.02 W/l-j
Form an oxygen plasma, by applying a density of
The SiN surface was oxidized to form an oxide layer 4. The discharge time was 20 minutes, and the substrate temperature was 320°C.
その後、酸素を除き、５ｉＨａ とＨ２混合ガスを導入
し、ａ−８ｉ膜５をプラズマＣＶＤにより堆積した。膜
厚は０．３ μｍである。その後、Ｐを２％程度ドー
プしたｎ型のａ−８ｉ膜６を堆積した膜厚は０．０３
ａｍである６次に、Ｃｒ７／ＡＱ８２重膜をそれぞれ
０．１ μｍと０．３ ｐｍ堆積し、ホトエツチン
グ法で加工し、ソースとドレイン電極とした後、ドライ
エツチング法でチャンネル部のｎ形ａ−５ｉ膜を除去し
た。さらに。Thereafter, oxygen was removed, a mixed gas of 5iHa and H2 was introduced, and an a-8i film 5 was deposited by plasma CVD. The film thickness is 0.3 μm. After that, an n-type a-8i film 6 doped with about 2% P was deposited, and the film thickness was 0.03.
Next, Cr7/AQ82 heavy films were deposited to a thickness of 0.1 μm and 0.3 pm, respectively, and processed using a photoetching method to form source and drain electrodes, and then dry etching was performed to form an n-type a layer in the channel portion. -5i film was removed. moreover.
ｐ−ＣＶＤ法でＳｉＮ膜９を保護膜として形成した。A SiN film 9 was formed as a protective film by p-CVD method.
この方法で形成したａ −Ｓ ｉ Ｔ Ｆ Ｔと従来方
法で形成したＴＰＴをそれぞれゲート電圧＋３０Ｖと一
３０Ｖを各１０００秒印加した時の閾値電圧のシフト量
を第２図に示す。本発明によるＴＰＴの方が、正方向、
負方向共に閾値電圧のシフト力）少ない。FIG. 2 shows the amount of shift in threshold voltage when gate voltages of +30 V and -30 V were applied for 1000 seconds to the a-S i T F T formed by this method and the TPT formed by the conventional method, respectively. In the TPT according to the present invention, in the positive direction,
Threshold voltage shift force (both in the negative direction) is small.
なお、この酸化層の厚さは数十人〜数百人の範囲にあり
、酸化層の形成によって移動度の劣化は見られなかった
。さらに、オフ電流は、従来方式のサンプルとほぼ同程
度もしくはそれ以下であった。The thickness of this oxidized layer was in the range of several tens to hundreds of layers, and no deterioration in mobility was observed due to the formation of the oxidized layer. Furthermore, the off-state current was approximately the same or lower than that of the conventional sample.
ここでは、酸化層の形成に酸素プラズマを用いたが、こ
こで使用するガスは酸素を数％以上含むＨｚもしくはＮ
ｚ 、 Ａ ｒ等でも同じような改善効果が見られた。Here, oxygen plasma was used to form the oxide layer, but the gas used here is Hz or N gas containing several percent or more of oxygen.
A similar improvement effect was seen with z, Ar, etc.
本発明によれば、ゲート絶縁膜ＳｉＮ表面に酸化層を形
成することにより、ａ−８ｉＴＰＴの安定性を大幅に改
善することが出来るので、例えば。According to the present invention, by forming an oxide layer on the surface of the gate insulating film SiN, the stability of a-8iTPT can be significantly improved.
これを用いた液晶デイスプレィの特性の長期信頼性を向
上できる効果がある。This has the effect of improving the long-term reliability of the characteristics of a liquid crystal display using this.
第１図は本発明の一実施例のＴＰＴの断面図。
第２図は本発明により効果を示す閾値電圧のシフト量を
表わす図である。
１・・・ガラス基板、２・・・Ｃｒ、３・・・ＳｉＮ、
４・・・酸 。
化層、５− ａ −３ｉ、６− ａ −Ｓ ｉのｎ層、
７・・・Ｃｒ、８−ＡＱ、９−８ｉＮ。
第 ／［！］FIG. 1 is a sectional view of a TPT according to an embodiment of the present invention. FIG. 2 is a diagram showing the shift amount of the threshold voltage that shows the effect of the present invention. 1...Glass substrate, 2...Cr, 3...SiN,
4...Acid. layer, 5-a-3i, 6-a-S i n layer,
7...Cr, 8-AQ, 9-8iN. No./[! ]
Claims (1)
非晶質水素化シリコンを半導体として積層した薄膜トラ
ンジスタにおいて、前記ゲート絶縁膜の前記非晶質化シ
リコン側表面に極めて薄い酸化層を有することを特徴と
する薄膜トランジスタ。 ２、前記酸化層が、前記ゲート絶縁膜の前記非晶質化シ
リコン側表面を酸化することにより形成されたものであ
ることを特徴とする特許請求の範囲第１項記載の薄膜ト
ランジスタ。[Claims] 1. In a thin film transistor in which amorphous hydrogenated silicon is laminated as a semiconductor on a gate insulating film made of a compound of silicon and nitrogen, an extremely thin film is formed on the surface of the amorphous silicon side of the gate insulating film. A thin film transistor characterized by having an oxide layer. 2. The thin film transistor according to claim 1, wherein the oxide layer is formed by oxidizing the surface of the gate insulating film on the amorphous silicon side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27014187A JPH01114080A (en) | 1987-10-28 | 1987-10-28 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27014187A JPH01114080A (en) | 1987-10-28 | 1987-10-28 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01114080A true JPH01114080A (en) | 1989-05-02 |
Family
ID=17482117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27014187A Pending JPH01114080A (en) | 1987-10-28 | 1987-10-28 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01114080A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198694A (en) * | 1990-10-05 | 1993-03-30 | General Electric Company | Thin film transistor structure with improved source/drain contacts |
| KR100282425B1 (en) * | 1997-10-10 | 2001-04-02 | 김영환 | Method for fabricating of capacitor |
-
1987
- 1987-10-28 JP JP27014187A patent/JPH01114080A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198694A (en) * | 1990-10-05 | 1993-03-30 | General Electric Company | Thin film transistor structure with improved source/drain contacts |
| US5362660A (en) * | 1990-10-05 | 1994-11-08 | General Electric Company | Method of making a thin film transistor structure with improved source/drain contacts |
| KR100282425B1 (en) * | 1997-10-10 | 2001-04-02 | 김영환 | Method for fabricating of capacitor |
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