JPS5854652A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5854652A
JPS5854652A JP56154192A JP15419281A JPS5854652A JP S5854652 A JPS5854652 A JP S5854652A JP 56154192 A JP56154192 A JP 56154192A JP 15419281 A JP15419281 A JP 15419281A JP S5854652 A JPS5854652 A JP S5854652A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
solder
back surface
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56154192A
Other languages
Japanese (ja)
Inventor
Kuniyasu Asada
浅田 邦保
Yasushi Nakamura
靖 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56154192A priority Critical patent/JPS5854652A/en
Publication of JPS5854652A publication Critical patent/JPS5854652A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To efficiently manufacture a semiconductor pellet having a solder layer on he back surface by forming a photoresist film along a line for cutting and isolating the back surface of a semiconductor wafer into semiconductor elements. CONSTITUTION:A through hole 3 which reaches from the front surface 1a to the back surface 1b of a semiconductor wafer 1 formed with semiconductor elements 2 is formed partly of a line to be cut and isolated. A photoresist film 4 is formed in a lattice shape along the line indexed from the hole 3. Subsequently, an ohmic metallic layer 5 is formed on the overall surface of the back surface 1b, and a solder paste layer 6 is formed on the overall upper surface of the layer 5. Thereafter, when the wafer 1 is heated by the melting temperature of the layer 6, the film 4 is burnt and lost, and the layer 5 is also vanished, thereby exposing the silicon base of the wafer 1. Accordingly, molten solder is agglomerated, and is cooled to form a solder layer 7 insularly on the layer 5. Thus, the wafer can be readily cut.

Description

【発明の詳細な説明】 この発明は、裏面に半田層を有する半導体装置の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a solder layer on its back surface.

一般に、トランジスタ等の半導体装置は、加熱したステ
ムあるいはリードフレーム等の放熱板上に半田片を供給
してこの半田片を溶融せしめておき、溶融半田トに裏面
にオーミック金属層を有する半導体ペレットを載置して
、この半導体ペレットを半田層を介して放熱板に固着し
て製造されている。ところで、このように半田片を溶融
してから半導体ペレットを供給する方法は、溶融した半
田層の表面に酸化膜等が形成されて、単に溶融半田層上
に半導体ペレットを供給するのみでは、半導体ペレット
と放熱板との固着が不完全になる。
Generally, semiconductor devices such as transistors are manufactured by supplying solder pieces onto a heated stem or a heat sink such as a lead frame, melting the solder pieces, and applying semiconductor pellets having an ohmic metal layer on the back surface to the molten solder. The semiconductor pellet is placed on the heat dissipation plate and fixed to the heat sink via a solder layer. By the way, this method of melting solder pieces and then supplying semiconductor pellets may result in the formation of an oxide film, etc. on the surface of the melted solder layer. The adhesion between the pellet and the heat sink becomes incomplete.

このため、従来はスクラブと称して半導体ペレットを溶
融半田層上に載置したのち?〜3回回動動作を与えたり
、あるいけ半導体ペレットを供給する直前に溶融半田層
の表面を引掻俸で引掻いて・酸化膜等を除去するように
している。しかLながら、このような方法では半導体ベ
レット固着工程に時間がかかり、量産上問題があった。
For this reason, in the past, semiconductor pellets were placed on the molten solder layer, which was called scrubbing. The molten solder layer is rotated three times, and the surface of the molten solder layer is scratched with a scraper to remove oxide films and the like just before supplying the semiconductor pellets. However, in such a method, the process of fixing the semiconductor pellet takes time, which poses a problem in mass production.

そこで、最近半導体ベレットの裏面に予備半田層を形成
しておき、この半導体ペレットをその裏面を下側に向け
て加熱された放熱板上に供給して、前記半導体ペレット
によるスクラブ動作または引J棒による引掻き動作なし
に半導体ペレットを放^板に固着する方法が提案されて
いる。
Therefore, a preliminary solder layer has recently been formed on the back surface of a semiconductor pellet, and the semiconductor pellet is supplied onto a heated heat sink with the back surface facing downward, and the semiconductor pellet is used for scrubbing or pulling a J rod. A method has been proposed for fixing semiconductor pellets to a radiation plate without the scratching action.

上記のような裏面に半田層を有する半導体ペレットを製
造する場合、予め半導体ウェーへの裏面全面に半田層を
形成し又おくと、これを個々の半導体ペレットに切断分
離するのは容易でない。何故なら、半導体ウェーハを薄
いブレードを用いて完全切断しようとする場合、半導体
ウェーハの裏面全面に半田層を形成しておくと、半田層
は軟らかいのと、表面電極に比較し1相当に厚いため、
ブレードが目詰りし、切断が不可能ないし著しく困鑓に
なるからである。一方、″半導体ウェーへの表面側から
半導体ウェーへの厚さの中途まで溝を形成したのち、半
導体ウェー八に撓屈力を作用させて半導体ペレットを製
造しようとする場合は、軟らかくてしかも厚い半田層が
うまく切断できず、半導体ペレット同士が半田層を介し
て連結した。
When manufacturing semiconductor pellets having a solder layer on the back surface as described above, if a solder layer is previously formed on the entire back surface of the semiconductor wafer, it is not easy to cut and separate the solder layer into individual semiconductor pellets. This is because when attempting to completely cut a semiconductor wafer using a thin blade, if a solder layer is formed on the entire back surface of the semiconductor wafer, the solder layer is soft and is considerably thicker than the surface electrode. ,
This is because the blade becomes clogged, making cutting impossible or extremely difficult. On the other hand, when attempting to manufacture semiconductor pellets by applying bending force to the semiconductor wafer after forming grooves from the surface side of the semiconductor wafer to the middle of the thickness of the semiconductor wafer, it is difficult to produce semiconductor pellets that are soft and thick. The solder layer could not be cut properly, and the semiconductor pellets were connected to each other through the solder layer.

いわゆるアベック不良を生じるからである。This is because so-called avec defects occur.

そnゆえに、この発明の主たる目的は、裏面に半田層を
有する半導体ペレットを能率良く製造する方法を提供す
ることである。
Therefore, the main object of the present invention is to provide a method for efficiently manufacturing semiconductor pellets having a solder layer on the back surface.

この発明を要約すると、半導体ウェーへの裏面の各半導
体素子に切断分離する線に沿ってフォトレジスト膜を形
成したのち、このフォトレジスト膜上を含む半導体ウェ
ーへの裏面全面にオーミック金属層を形成し、このオー
ミック金属層の上に半田ペースト層を形成し、半導体ウ
ェーハを加熱して前記半田ペースト層を加熱溶融して半
田層を形成してから、半導体ウェーハを前記線に沿って
切断分離して半導体ペレットを得るようにしたことを特
徴とするものである。
To summarize this invention, a photoresist film is formed on the back surface of a semiconductor wafer along the cutting and separating lines for each semiconductor element, and then an ohmic metal layer is formed on the entire back surface of the semiconductor wafer, including on the photoresist film. Then, a solder paste layer is formed on the ohmic metal layer, and the semiconductor wafer is heated to melt the solder paste layer to form a solder layer, and then the semiconductor wafer is cut and separated along the lines. The invention is characterized in that semiconductor pellets are obtained by

以F1この発明の一実施例を図面により説明する。まず
、第1図に示すように、多数の半導体素子2を形成した
半導体ウェーハlを用意し、その表面1aの各半導体素
子2,2間の切断分離予定機の一部にレーザービームを
照射して裏面1bに達する貫通孔3を設け、この貫通孔
3を基準にして裏面1 b4mの切断予定梅を割り出し
1この切断予定線に沿ってフォトレジスト膜4を格子状
に形成する。このフォトレジスト膜4はスクリーン印刷
法等によって直接格子状に形成してもよいし、周知のよ
うに半導体ウェー八lの裏面1bの全面にフォトレジス
ト膜を形成したのち、露光および現像処理によって格子
状にフォトレジスト膜4を一存せしめて形成してもよい
。次に第2図に示すように、この半導体ウェー八1の裏
面1bの全面にオーミック金属層5を形成する。このオ
ーミツ゛り金属層5は従来と同様のものでよく、例えば
クロム、ニラクル+ m l銀を順次蒸着して形成する
ことができる。こののち、第3図に示すように1半導体
ウェーハlの裏面1bの全面に半田ペーストをスクリー
ン印刷等により均一の厚さに塗布して半田ペースト層6
を形成する。次■で、この半導体ウェーハlを半田ペー
スト層6の溶融温度。
Hereinafter, an embodiment of the present invention will be explained with reference to the drawings. First, as shown in FIG. 1, a semiconductor wafer l having a large number of semiconductor elements 2 formed thereon is prepared, and a laser beam is irradiated onto a portion of the surface 1a of the cutting and separating machine between each semiconductor element 2. A through hole 3 is provided to reach the back surface 1b, and a cut plan on the back surface 1b4m is determined based on the through hole 3, and a photoresist film 4 is formed in a lattice shape along the cut plan line. This photoresist film 4 may be directly formed in a grid shape by screen printing or the like, or as is well known, a photoresist film is formed on the entire back surface 1b of the semiconductor wafer 8l, and then a grid pattern is formed by exposure and development processing. Alternatively, the photoresist film 4 may be formed in a manner similar to that shown in FIG. Next, as shown in FIG. 2, an ohmic metal layer 5 is formed on the entire back surface 1b of this semiconductor wafer 1. This ohmic metal layer 5 may be the same as the conventional one, and can be formed, for example, by sequentially depositing chromium, niracle+ml silver. Thereafter, as shown in FIG. 3, solder paste is applied to the entire back surface 1b of one semiconductor wafer l to a uniform thickness by screen printing or the like to form a solder paste layer 6.
form. Next, in step (2), this semiconductor wafer l is heated to the melting temperature of the solder paste layer 6.

例えば350℃程度で加熱して、半田ペースト層6を溶
融しバインダ成分を焼失せしめて、第4v!1に示すよ
うに、半田層7を形成する。このとき、前記加熱温度に
よつぞフォトレジスト膜番が焼失して、その上のオーミ
ック金属層541消失してしまい半導体ウェー711の
シリコン素地カミ露出するので、溶融半田がシリコン素
地に対し又は濡れないこと、およびオーミック金属層6
上の溶融半田の凝集力によって、溶融半田がオーミック
金属層5上にのみ凝集する結果、そのま−冷却すると、
半田層7はオーミック金属層5上にのみに島状に。
For example, the solder paste layer 6 is heated at about 350° C. to melt the binder component and burn out the binder component. 1, a solder layer 7 is formed. At this time, the photoresist film is burnt out due to the heating temperature, and the ohmic metal layer 541 thereon disappears, exposing the silicon substrate of the semiconductor wafer 711, so that the molten solder does not touch or wet the silicon substrate. and ohmic metal layer 6
Due to the cohesive force of the molten solder above, the molten solder aggregates only on the ohmic metal layer 5, and as a result, when it is cooled,
The solder layer 7 is formed in an island shape only on the ohmic metal layer 5.

−rなわち各半導体素子2の形状にしたカミって独立状
に形成され、切断予定線上にはオーミック金属層5およ
び半田層7がない米導体つェー/%1力監得られる。最
後に、この半導体ウヱーノ11を切断予定騨の中心、す
なわち第4図の−・点鎖線位置カミら切断分離すると、
第5図に示すような、裏面に半田層7を有する半導体ペ
レット2a力;得られる。
In other words, the wires in the shape of each semiconductor element 2 are formed independently, and the ohmic metal layer 5 and solder layer 7 are not present on the cutting line, so that a conductive wire can be observed. Finally, this semiconductor unit 11 is cut and separated from the center of the edge to be cut, that is, at the position shown by the dashed dotted line in FIG.
A semiconductor pellet 2a having a solder layer 7 on the back surface as shown in FIG. 5 is obtained.

このとき1半導体ウエーノ箋1の切断予定線上にオーミ
ック金属層5および半田層7カ;存在しないので、ダイ
シングブレードにより半導体ウエーノ11を完全に切断
するにしても、半田層7を切断する場合ノj−うなダイ
シングブレードの目詰りの問題を生じないで極めて容易
に切断できるし、あるいは半導体ウェーハlの厚さの中
途までの溝を形成したのち半導体ウェーハlに撓屈力を
作用させて前記溝部分から切断するにしても、軟い半田
層7によって半導体ベレン)2a同士が連結する。いわ
ゆるアベック不良も皆無となる。
At this time, the ohmic metal layer 5 and the solder layer 7 do not exist on the planned cutting line of the semiconductor wafer 1, so even if the semiconductor wafer 11 is completely cut with the dicing blade, when the solder layer 7 is cut, the ohmic metal layer 5 and the solder layer 7 are not present. - It can be cut very easily without causing the problem of clogging of the dicing blade, or after forming a groove halfway through the thickness of the semiconductor wafer l, a bending force is applied to the semiconductor wafer l to cut the groove. Even when cutting from the base, the semiconductor belenium 2a are connected to each other by the soft solder layer 7. There are no so-called Abec defects.

なお、上記実施例においては、半導体ウェーハ1の裏面
1bのオーミック金属層5上全面に半田ペースト層6を
形成する場合について説明したが(第3図参照)、この
ようにすれば半田ペースト層6を形成する際に、目合せ
作業が不要になる利点がある。ただし、もし必要ならば
、目合せを行なって半田ペーストをフォトレジスト膜4
の上部分を除いて塗布して1島状の半田レジスト層6を
形成するようにしてもよい。
In the above embodiment, the solder paste layer 6 is formed entirely on the ohmic metal layer 5 on the back surface 1b of the semiconductor wafer 1 (see FIG. 3). There is an advantage that alignment work is not required when forming the . However, if necessary, align and apply the solder paste to the photoresist film 4.
Alternatively, the solder resist layer 6 may be coated except for the upper portion of the solder resist layer 6 to form one island-shaped solder resist layer 6.

この発明は以りのように、多数の半導体素子を形成した
半導体ウエーノ1の裏面のL記各半導体素子に切断分離
する線に沿ってフォトレジスト膜を形成°す為工程と、
この半導体ウェーへの前記フォトレジスト膜上を含む裏
面全面にオーミック金属層を形成する工程と、前記オー
ミック金属層の上に半田ペースト層を形成する工程と、
半導体ウェーハを加熱して前記半田ペースト層を溶融し
て半田層を形成する工程と、半導体ウエーノ1を前記線
に沿って切断分離して半導体ペレットを得る工程とを含
むから、裏面に半田層を有する半導体ペレットを容易に
製造できるという効果を奏する。
The present invention includes the steps of forming a photoresist film along the lines L for cutting and separating each semiconductor element on the back surface of a semiconductor wafer 1 on which a large number of semiconductor elements are formed;
a step of forming an ohmic metal layer on the entire back surface of the semiconductor wafer including the photoresist film, and a step of forming a solder paste layer on the ohmic metal layer;
The method includes a step of heating the semiconductor wafer to melt the solder paste layer to form a solder layer, and a step of cutting and separating the semiconductor wafer 1 along the lines to obtain semiconductor pellets. It is possible to easily manufacture semiconductor pellets having the following properties.

【図面の簡単な説明】[Brief explanation of drawings]

第1(2)ないし第6図はこの発明の一実施例を説明す
るための各段階における半導体ウエーノ1ないし半導体
ペレットの断面図である。 1・・・・・・半導体ウェーハ、 1b・・・・・・裏面、 2・・・・・・半導体素子1 4・・・・・・フォトレジスト膜、 5・・・・・・オーミック金属層、 60.911.半田ペースト層、 ヴ・・・・・・半田層。 第1図 第2図 第3図 第4図 第5図 a ノ
1(2) to 6 are cross-sectional views of the semiconductor wafer 1 to the semiconductor pellet at each stage for explaining an embodiment of the present invention. 1...Semiconductor wafer, 1b...Back surface, 2...Semiconductor element 1 4...Photoresist film, 5...Ohmic metal layer , 60.911. Solder paste layer, V...Solder layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 a

Claims (1)

【特許請求の範囲】[Claims] 多数の半導体素子を形成した半導体ウエーノ\の裏面の
上記各半導体素子に切断分離する線に沿ってフォトレジ
スト膜を形成する工程と、この半導体ウェーへの前記フ
オトレジス)Ml上を含む裏面にオーミック金属層を形
成する工程と、前記オーミック金属層の上に半田ペース
ト層を形成する工程′と、半導体ウエーノ・を加熱して
前記半田ペースト層を溶融して半田層を形成する工程と
、半導体ウェーハt−m配線に沿って切断分離し又半導
体ベレットを得る工程とを含む半導体装置の製造方法。
A step of forming a photoresist film on the back surface of a semiconductor wafer on which a large number of semiconductor devices are formed along the lines that cut and separate the semiconductor devices, and applying an ohmic metal to the back surface including the photoresist layer on the semiconductor wafer. a step of forming a solder paste layer on the ohmic metal layer; a step of heating a semiconductor wafer to melt the solder paste layer to form a solder layer; and a step of forming a solder layer on the semiconductor wafer. - A method for manufacturing a semiconductor device, including a step of cutting and separating along the m wiring and obtaining a semiconductor pellet.
JP56154192A 1981-09-28 1981-09-28 Manufacture of semiconductor device Pending JPS5854652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56154192A JPS5854652A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56154192A JPS5854652A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5854652A true JPS5854652A (en) 1983-03-31

Family

ID=15578843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56154192A Pending JPS5854652A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5854652A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03234033A (en) * 1990-02-09 1991-10-18 Rohm Co Ltd Manufacture of semiconductor device
JP2013157343A (en) * 2012-01-26 2013-08-15 Tokyo Seimitsu Co Ltd Wafer processing method and system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03234033A (en) * 1990-02-09 1991-10-18 Rohm Co Ltd Manufacture of semiconductor device
JP2013157343A (en) * 2012-01-26 2013-08-15 Tokyo Seimitsu Co Ltd Wafer processing method and system

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