JPS60120540A - Forming method of bump electrode - Google Patents
Forming method of bump electrodeInfo
- Publication number
- JPS60120540A JPS60120540A JP58229283A JP22928383A JPS60120540A JP S60120540 A JPS60120540 A JP S60120540A JP 58229283 A JP58229283 A JP 58229283A JP 22928383 A JP22928383 A JP 22928383A JP S60120540 A JPS60120540 A JP S60120540A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- metal mask
- bump
- mask
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はバンプ電極の形成方法に関する。[Detailed description of the invention] The present invention relates to a method for forming bump electrodes.
半導体装置において電極となるアルミニウム膜上にはん
だバンプを形成する方法として従来用いられている方法
には、（１）メタルマスクを半導体基板上に載置し、こ
の上にバンプ形成金属であるクロム、金、はんだを蒸着
しはんだバンプを選択的に形成する蒸着法、（２）はん
だバンプ形成領域に対応する部分に窓穴を有するメタル
マスクを半導体基板上に載置し、はんだポールをこのメ
タルマスク上にころがし、その幾つかをはんだバンプ形
成領域上に移動させ、加熱処理によりあらかじめ形成し
ておいたバンプ接合金属と接着させ、はんだバングを形
成するいわゆるはんだボール法、（３）半導体基板全面
にバンプ接合金属の一部となる金属膜を被着させ、その
後、フォトレジストを顔布し通常の方法によりバンプ形
成領域に窓穴を形成し電気めっきにより銅めっき層を形
成し、さらにはんだめっき層を形成した後、レジストを
除去し、不要なバンプ接合金属膜をエツチングによって
除去し、はんだバンプを形成するいわゆる電気めっき法
がある。Conventionally used methods for forming solder bumps on aluminum films that serve as electrodes in semiconductor devices include (1) placing a metal mask on a semiconductor substrate, and applying chromium, which is a bump-forming metal, on the metal mask; A vapor deposition method in which gold and solder are vapor-deposited to selectively form solder bumps. (2) A metal mask having window holes in the area corresponding to the solder bump formation area is placed on the semiconductor substrate, and the solder poles are attached to the metal mask. (3) The so-called solder ball method, in which some of the solder bumps are rolled onto the solder bump formation area and bonded to the bump bonding metal previously formed by heat treatment to form solder bangs. A metal film that will become part of the bump bonding metal is deposited, then a photoresist is applied, a window hole is formed in the bump formation area by the usual method, a copper plating layer is formed by electroplating, and then a solder plating layer is formed. There is a so-called electroplating method in which after forming a solder bump, the resist is removed and an unnecessary bump bonding metal film is removed by etching to form a solder bump.
しかし、（１）蒸着法においては、半導体基板とメタル
マスクの接触が不完全なために、そのすき間にはんだバ
ンプを構成する蒸着金属がまわシ込みバンプ形成領域を
メタルマスクの窓穴通シに制御することが困難であった
。また、蒸着温度において、はんだ成分である鉛及び錫
の蒸気圧に大きな差があシ、鉛が優先的に蒸着されるた
め、低融点はんだを一度に蒸着することが困難で、所望
の融点のはんだバンプを形成することができなかった（
２）はんだポール法においては、メタルマスクのバンプ
形成領域に対応する窓穴にはんだボーＩしを１個ずつ確
実に入れることが困難で、窓穴に２個のはんだポールが
入ってしまうという問題があった。However, (1) in the vapor deposition method, because the contact between the semiconductor substrate and the metal mask is incomplete, the vapor-deposited metal that makes up the solder bumps is injected into the gap and the bump formation area is passed through the window hole of the metal mask. It was difficult to control. In addition, there is a large difference in the vapor pressure of the solder components lead and tin at the deposition temperature, and lead is preferentially deposited, making it difficult to deposit low melting point solder all at once, and achieving the desired melting point. Unable to form solder bumps (
2) In the solder pole method, it is difficult to reliably insert each solder ball into the window hole corresponding to the bump formation area of the metal mask, resulting in two solder balls entering the window hole. was there.
（３）電気めっき法においては、大面積の半導体基板た
とえば４インチシリコンウェハ上にはんだめっきを行な
うと、電流密度およびめっき液の流れが不均一になるだ
め、均一な厚さのはんだめっき層をウェハ全面に形成す
ることが困難でおった０まだ、同様な理由から、ウェハ
全面に一定の組成のはんだめっき層を形成することが難
しいという欠点があった。(3) In the electroplating method, when solder plating is performed on a large area semiconductor substrate, such as a 4-inch silicon wafer, the current density and flow of the plating solution become uneven, so a solder plating layer of uniform thickness is not possible. However, for the same reason, it was difficult to form a solder plating layer with a constant composition over the entire wafer.
本発明の目的は、大面積の半導体基板上に均一な高さ、
組成および形状を有するはんだバンプを量産において再
現性よく形成し得る技術を提供参ることである。上記目
的を達成するだめの本発明の要旨は、２枚の同一パター
ンを有するメタルマスクを重ね合わせ、これを半導体基
板上に載置し、はんだペーストをメタルマスク上に塗布
し、メタルマスクの窓穴を通してバンプ形成領域にはん
だペーストを被着させ、下方のメタルマスクを半導体基
板に固定し、上方のメタフレマスクをマスク面内で移動
させ、バンプ形成領域に被着させたはんだペーストの厚
さを制御したことを特徴とするバンプ電極の形成方法に
ある。The object of the present invention is to provide a uniform height on a large area semiconductor substrate.
The purpose of the present invention is to provide a technology that enables mass production of solder bumps having the same composition and shape with good reproducibility. The gist of the present invention to achieve the above object is to overlap two metal masks having the same pattern, place them on a semiconductor substrate, apply solder paste on the metal masks, and apply solder paste to the metal masks. Solder paste is applied to the bump formation area through the hole, the lower metal mask is fixed to the semiconductor substrate, and the upper metal mask is moved within the mask plane to measure the thickness of the solder paste applied to the bump formation area. The present invention provides a method for forming a bump electrode characterized in that it is controlled.
以下、本発明実施例を図面に沿って具体的に説明する。Embodiments of the present invention will be specifically described below with reference to the drawings.
第１図に示すように、アルミニラム電甑上に絶縁保護膜
４に窓穴を通常の方法であけアルミニウム゛醒極６を露
出させる。As shown in FIG. 1, a window hole is made in the insulating protective film 4 on the aluminum battery box using the usual method to expose the aluminum cathode 6.
このような半導体基板上１に、第２図に示すように２枚
の同一パターンを有する第１のメタルマスク５と第２の
メタルマスク６を、バンプ形成領域とメタルマスクの窓
穴の位置合わせを行なって載置する。次に、真空被着法
によりて、第１のノ（ンプ接合金属膜７例えばクロム膜
と第２０）くンプ按合金属膜８例えば銅膜をバンプ形成
領域に選択的に被着させる。On such a semiconductor substrate 1, as shown in FIG. 2, two first metal masks 5 and a second metal mask 6 having the same pattern are placed, and the bump formation area and the window holes of the metal masks are aligned. and place it. Next, the first bump bonding metal film 7, for example, a chromium film, and the twentieth bump bonding metal film 8, for example, a copper film are selectively deposited on the bump forming region by a vacuum deposition method.
次に第３図に示すように、ベーヌト状はんだ例えば錫６
０％、鉛４０チ１組成のはんだ粒子とはんだ用フラック
スからなるはんだペースト９をすくなくとも第１のメタ
ルマスク５の厚さより厚く塗布する。Next, as shown in FIG.
A solder paste 9 consisting of solder particles and solder flux having a composition of 0% lead and 40% lead is applied at least to a thickness greater than the thickness of the first metal mask 5.
この後、第４図に示すように、第１のメタルマスク５の
上面に沿って第２のメタルマスク６を移動させ、はんだ
ペースト９が充填された第１のメタルマスク５の窓穴を
覆う。この操作によってノ（ンプ形成領域に第１０メタ
μマスク５と同じ厚さのはんだペースト層９Ａが形成さ
れ、余分なはんだペースト９Ｂは第２のメタルマスク６
と共に移動させる。After this, as shown in FIG. 4, the second metal mask 6 is moved along the upper surface of the first metal mask 5 to cover the window hole of the first metal mask 5 filled with the solder paste 9. . Through this operation, a solder paste layer 9A having the same thickness as the tenth meta-μ mask 5 is formed in the non-bump forming area, and the excess solder paste 9B is transferred to the second metal mask 6.
move with it.
次に第５図に示すように、第１のメタルマスク５および
第２のメタルマスク６を取り去り、）くンプ形成領域の
みにはんだペースト層９Ａを残す。Next, as shown in FIG. 5, the first metal mask 5 and the second metal mask 6 are removed, leaving the solder paste layer 9A only in the bump formation area.
この後、第６図に示すように、はんだ融点以上の温度例
えば２５０℃にはんだペースト層を加熱し、半球状はん
だパン１９′をバンプ接合金属８の上に形成する０
以上述べたような本発明の構成によれば下記のような目
的が達成できる。Thereafter, as shown in FIG. 6, the solder paste layer is heated to a temperature above the solder melting point, for example, 250° C., and a hemispherical solder pan 19' is formed on the bump bonding metal 8. According to the configuration of the invention, the following objects can be achieved.
（１）はんだペーストをはんだ材料として使うため所望
の組成（融点）のはんだバンプを形成することができる
。(1) Since solder paste is used as the solder material, solder bumps with a desired composition (melting point) can be formed.
（２）はんだバンプの高さおよび形状をメタルマスクの
厚さ及び窓穴の形状によって制御するので、均−な高さ
および形状を有するはんだバンプを再現性よく形成する
ことができる。(2) Since the height and shape of the solder bump are controlled by the thickness of the metal mask and the shape of the window hole, solder bumps having uniform height and shape can be formed with good reproducibility.
（３）はんだバンプの大きさおよびバンプの間隔はメタ
ルマスクの窓穴およびその間隔で制御するだめ、バンプ
の大きさおよびバンプの間隔をメタルマスクの窓穴の作
製上の限界にまで、縮少することが可能であり、高集積
化を指向する半導体装置にはんだバンプを形成するのに
適する。(3) The size of the solder bumps and the spacing between the bumps must be controlled by the window holes in the metal mask and the spacing between them, so reduce the size of the bumps and the spacing between the bumps to the manufacturing limit of the metal mask window holes. This method is suitable for forming solder bumps in semiconductor devices that aim for higher integration.
本発明は、突流例で述べたはんだバンプに限定すること
なく、はんだ材料として鉛粒子から構成される鉛ペース
トを使用すれば鉛バンプの形成にも適用し得る。The present invention is not limited to the solder bumps described in the rush example, but can also be applied to the formation of lead bumps if a lead paste made of lead particles is used as the solder material.
第１図から第６図までは本発明のバンプ電極の形成方法
をル６明するための工程１嗅の断面図である。
１・・・・・・半導体基板、２・・・・・・絶縁膜、３
・・・・・・アルミニウム電極、４・・・・・・保護膜
、５・・・・・・第１のメタルマフ、り、６・・・・・
・第２のメタルマスク、７・・・・・・第１のバンプ接
合金属 ７＋・・・・・・第２のメタルマスクに被着し
た第１のバンプ接合金属、８・・・・・・第２のバンプ
接合金属、８′・・・・・・第２のメタルマスクに被着
した第２のバンプ接合金属、９・・・・・・はんだペー
スト、９１・・・・・半球状はんだノくンプ以上
出願人 セイコー電子工業株式会社
代理人弁理士 最 上 務
第１図
第４図
第５図
ｊＩ乙図1 to 6 are cross-sectional views of step 1 for explaining the method of forming a bump electrode of the present invention. 1... Semiconductor substrate, 2... Insulating film, 3
...Aluminum electrode, 4...Protective film, 5...First metal muff, 6...
- Second metal mask, 7...First bump bonding metal 7+...First bump bonding metal deposited on second metal mask, 8... Second bump bonding metal, 8'...Second bump bonding metal deposited on the second metal mask, 9...Solder paste, 91...Semispherical solder Nokumpu and above Applicant Seiko Electronic Industries Co., Ltd. Representative Patent Attorney Mogami Figure 1 Figure 4 Figure 5 jI Otsu Figure
Claims (1)
のパターンの窓穴を有する第１のメタルマスクを固定し
、第１のメタルマスクと同じパターンを有する第２のメ
タルマスクを第１のメタルマスクの上面に窓穴を一致さ
せて重ね、はんだペーストを第２のメタルマスクの上面
に塗布し、前記はんだペーストを前記半導体基板の電極
上に被着させる工程と、第２のメタルマスクを第１のメ
タルマスク上面にそって移動させ、第１のメタルマスク
の窓穴を第２のメタルマスで覆うことにより、前記半導
体基板の電極上に被着させた前記はんだペーストの厚さ
を制御する工程と、第１のメタルマスクと第２のメタル
マスクを取り去υ、前記半導体基板の電極上に一定の厚
さのはんだペースト層を形成する工程と、前記はんだペ
ースト層を加熱し半球状はんだ層とする工程とからなる
バンプ電極の形成方法。(1) A first metal mask having a desired pattern of window holes is fixed to one main surface of a semiconductor substrate on which bump electrodes are to be formed, and a second metal mask having the same pattern as the first metal mask is attached to the first metal mask. overlapping the upper surface of the metal mask with window holes aligned with each other, applying solder paste to the upper surface of the second metal mask, and depositing the solder paste on the electrode of the semiconductor substrate; The thickness of the solder paste deposited on the electrode of the semiconductor substrate is controlled by moving the solder paste along the upper surface of the first metal mask and covering the window hole of the first metal mask with a second metal mask. removing the first metal mask and the second metal mask, forming a solder paste layer of a certain thickness on the electrodes of the semiconductor substrate, and heating the solder paste layer to form a hemispherical shape. A method for forming a bump electrode, which comprises a step of forming a solder layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58229283A JPS60120540A (en) | 1983-12-05 | 1983-12-05 | Forming method of bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58229283A JPS60120540A (en) | 1983-12-05 | 1983-12-05 | Forming method of bump electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60120540A true JPS60120540A (en) | 1985-06-28 |
Family
ID=16889687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58229283A Pending JPS60120540A (en) | 1983-12-05 | 1983-12-05 | Forming method of bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60120540A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63156343A (en) * | 1986-12-20 | 1988-06-29 | Fujitsu Ltd | Metal mask for solder-bump formation |
| US5270253A (en) * | 1986-01-27 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Method of producing semiconductor device |
| US5536677A (en) * | 1994-12-01 | 1996-07-16 | Motorola, Inc. | Method of forming conductive bumps on a semiconductor device using a double mask structure |
-
1983
- 1983-12-05 JP JP58229283A patent/JPS60120540A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270253A (en) * | 1986-01-27 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Method of producing semiconductor device |
| JPS63156343A (en) * | 1986-12-20 | 1988-06-29 | Fujitsu Ltd | Metal mask for solder-bump formation |
| US5536677A (en) * | 1994-12-01 | 1996-07-16 | Motorola, Inc. | Method of forming conductive bumps on a semiconductor device using a double mask structure |
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