JPS5818928A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5818928A
JPS5818928A JP11803681A JP11803681A JPS5818928A JP S5818928 A JPS5818928 A JP S5818928A JP 11803681 A JP11803681 A JP 11803681A JP 11803681 A JP11803681 A JP 11803681A JP S5818928 A JPS5818928 A JP S5818928A
Authority
JP
Japan
Prior art keywords
resist
wafer
protrusion
protrusions
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11803681A
Other languages
Japanese (ja)
Inventor
Shoichi Fujisada
藤定 正一
Masami Kato
加藤 正美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11803681A priority Critical patent/JPS5818928A/en
Publication of JPS5818928A publication Critical patent/JPS5818928A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching

Abstract

PURPOSE:To smooth the surface of a semiconductor thin film substrate by using partial etching. CONSTITUTION:While rotating an epitaxial wafer 1 having protrusion 2 at high speed a resist 3 is dropped to the wafer surface. The resultant film covering the surface of the protrusion is far thinner than other portion of the film. This thinner film portion is selectively removed, then the protrusion is etched with the resist 3 applied as a mask, and finally the resist 3 is removed, making the surface without any protrusion available. Therefore, pour contact with a mask and mask damage can be avoided.

Description

【発明の詳細な説明】 本発明は薄膜基板、特にSi、GaAs等の半導体基板
上に薄膜を結晶成長させた基板(以後エビウェハーと呼
ぶ)K関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film substrate, particularly a substrate (hereinafter referred to as a shrimp wafer) K in which a thin film is crystal-grown on a semiconductor substrate such as Si or GaAs.

半導体基板上に薄膜を結晶成長させる場合、半導体基板
上の半導体物質のクズやゴミ等により形成されたエピウ
ェハーの表面に突起物が出来ていた。これらの突起物は
、エビウェハーを用いて半導体装置(以後、ウェハーと
呼ぶ)を製造する場合に、現在は大部分のウェハーがマ
スクを用いた写真蝕刻法によシ素子(以後ペレットと呼
ぶ)を製造しているために、写真蝕刻のためのマスクと
ウェハーの密着不良を引き起こし、ひいてはペレ、ドパ
ターンの形成不良となり、製品品質の低下及び生産性の
低下を′引き起こしていた。このため。
When a thin film is grown as a crystal on a semiconductor substrate, protrusions are formed on the surface of the epitaxial wafer due to scraps and dust of the semiconductor material on the semiconductor substrate. These protrusions are caused by the fact that when semiconductor devices (hereinafter referred to as wafers) are manufactured using shrimp wafers, currently most wafers are made by photolithography using a mask to produce semiconductor devices (hereinafter referred to as pellets). Due to the manufacturing process, poor adhesion between the mask for photoetching and the wafer occurs, which in turn leads to defective formation of patterns and deterioration of product quality and productivity. For this reason.

従来はエビウェハー表面を平坦にする方法として。Conventionally, this method was used to flatten the surface of shrimp wafers.

エビウェハー表面にある硬度以上の固型物平板を圧着す
る事により、不要な突起部分を押しつぶして除去してい
た。しかしながら、この方法では圧着時に押しつぶされ
た突起物の破片が該エビウェハー上に付着したり、ある
大きさ以上の突起物は完全に圧着する事が出来ず、突起
物を完全に除去する事が出来ない等の問題点があった。
Unnecessary protrusions were crushed and removed by crimping a solid plate with a hardness higher than that on the surface of the shrimp wafer. However, with this method, fragments of the protrusions crushed during crimping may adhere to the shrimp wafer, and protrusions larger than a certain size cannot be completely crimped, making it impossible to completely remove the protrusions. There were some problems such as not having one.

本発明は上記問題点を除去する事により、製品品質や向
上及び生産性の向上を図る事を目的としたエビウェハー
表面を平担にするための方法を提供するものである。
The present invention provides a method for flattening the surface of a shrimp wafer with the aim of improving product quality and productivity by eliminating the above-mentioned problems.

すなわち、本発明は部分蝕刻法を用いて平坦にしたもの
であり、以下に本発明を実施例によシ説明する。第1図
(a)は突起物のあるエピウェハーの平面図、(b)は
その側面図である。第2図は本発明の実施例を示す上記
エビウェハーの断面図である。
That is, the present invention uses a partial etching method to achieve flattening, and the present invention will be explained below using examples. FIG. 1(a) is a plan view of an epiwafer with protrusions, and FIG. 1(b) is a side view thereof. FIG. 2 is a cross-sectional view of the above shrimp wafer showing an embodiment of the present invention.

まづ、突起物2のあるエビウェハーlの表面に耐腐蝕性
物質(以下、レジストと呼ぶ)3をエビウェハーを高速
で回転させながらレジストを滴下する事により塗布する
。本方法による塗布では突起物表面には他の部分に比較
し相当薄い膜しか付着しない(第2図(a))。次に、
突起物20表面に付着した薄いレジストが除去されるま
でウェハー表面のレジストを除去する(第2図(b))
。この時、他の部分のレジストも除去されるがレジスト
膜厚が厚いので一部表面層が除去されるのみで大部分が
残る0次に、該レジスト3を保護膜として突起物を蝕刻
して除去する(第2図(C))。最後に、レジスト3を
除去すると不要な突起物のみが除去されエビウェハー表
面の突起はなくなる。
First, a corrosion-resistant substance (hereinafter referred to as resist) 3 is applied to the surface of the shrimp wafer l having the projections 2 by dropping the resist while rotating the shrimp wafer at high speed. In coating according to this method, only a considerably thinner film is deposited on the surface of the protrusion than on other parts (FIG. 2(a)). next,
The resist on the wafer surface is removed until the thin resist attached to the surface of the protrusion 20 is removed (FIG. 2(b)).
. At this time, other parts of the resist are also removed, but since the resist film is thick, only a part of the surface layer is removed and most of it remains.Next, the protrusions are etched using the resist 3 as a protective film. (Fig. 2(C)). Finally, when the resist 3 is removed, only the unnecessary protrusions are removed and the protrusions on the surface of the shrimp wafer disappear.

以上の様に本発明によれば突起物の大きさに関係なくエ
ビウェハー表面の突起物を除去出来、該突起物により引
き起こされていたマスクとの密着不良、及びマスクへの
傷等の問題が解消され、ペレット製品品質及び生産性の
向上を図る事が出来る。
As described above, according to the present invention, protrusions on the shrimp wafer surface can be removed regardless of the size of the protrusions, and problems such as poor adhesion with the mask and scratches on the mask caused by the protrusions are resolved. This makes it possible to improve pellet product quality and productivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は表面に突起があるエビウェハーの平面図
、(b)はその断面図である。第2図(a)〜(d)は
本発明の一実施例による製造方法を示す断面図である。 1・・・・・・結晶成長させた半導体基板(エビウェハ
ー)、2・・・・・・エビウェハー上に出来た突起物、
3・・・・・・レジスト。
FIG. 1(a) is a plan view of a shrimp wafer having protrusions on its surface, and FIG. 1(b) is a sectional view thereof. FIGS. 2(a) to 2(d) are cross-sectional views showing a manufacturing method according to an embodiment of the present invention. 1...Semiconductor substrate (shrimp wafer) on which crystals have been grown, 2...Protrusions formed on the shrimp wafer,
3...Resist.

Claims (1)

【特許請求の範囲】 半導体薄膜基板の表面の平坦度を得る場合に。 部分蝕刻法を用いる事を特徴とする半導体装置の製法。[Claims] For obtaining surface flatness of semiconductor thin film substrates. A method for manufacturing a semiconductor device characterized by using a partial etching method.
JP11803681A 1981-07-28 1981-07-28 Manufacture of semiconductor device Pending JPS5818928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11803681A JPS5818928A (en) 1981-07-28 1981-07-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11803681A JPS5818928A (en) 1981-07-28 1981-07-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5818928A true JPS5818928A (en) 1983-02-03

Family

ID=14726456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11803681A Pending JPS5818928A (en) 1981-07-28 1981-07-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5818928A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019632A1 (en) * 2001-08-23 2003-03-06 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
JP2008300650A (en) * 2007-05-31 2008-12-11 Sumitomo Electric Ind Ltd Manufacturing method for semiconductor light element
US7528075B2 (en) * 2004-02-25 2009-05-05 Hrl Laboratories, Llc Self-masking defect removing method
CN106025000A (en) * 2016-06-02 2016-10-12 天津三安光电有限公司 Handling method for epitaxy defect

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019632A1 (en) * 2001-08-23 2003-03-06 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
US7056789B2 (en) 2001-08-23 2006-06-06 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
US7528075B2 (en) * 2004-02-25 2009-05-05 Hrl Laboratories, Llc Self-masking defect removing method
US7951719B2 (en) 2004-02-25 2011-05-31 Hrl Laboratories, Llc Self-masking defect removing method
JP2008300650A (en) * 2007-05-31 2008-12-11 Sumitomo Electric Ind Ltd Manufacturing method for semiconductor light element
CN106025000A (en) * 2016-06-02 2016-10-12 天津三安光电有限公司 Handling method for epitaxy defect

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