JPH0290529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0290529A JPH0290529A JP24102288A JP24102288A JPH0290529A JP H0290529 A JPH0290529 A JP H0290529A JP 24102288 A JP24102288 A JP 24102288A JP 24102288 A JP24102288 A JP 24102288A JP H0290529 A JPH0290529 A JP H0290529A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- wafer
- electrode
- hole
- dry film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 229910000679 solder Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000000694 effects Effects 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910020816 Sn Pb Inorganic materials 0.000 abstract 1
- 229910020922 Sn-Pb Inorganic materials 0.000 abstract 1
- 229910008783 Sn—Pb Inorganic materials 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 230000001808 coupling effect Effects 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 208000025174 PANDAS Diseases 0.000 description 4
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 4
- 240000004718 Panda Species 0.000 description 4
- 235000016496 Panda oleosa Nutrition 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の入出力電極の形成方法に係り
、特にTAB?71Jツブチップ接続に好適なはんだパ
ンダ形成法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for forming input/output electrodes of a semiconductor integrated circuit, and particularly relates to a method for forming input/output electrodes of a semiconductor integrated circuit. This invention relates to a solder panda forming method suitable for 71J round chip connection.
従来の装置は、マイクロデバイセス、1987年。 The conventional device was manufactured by Micro Devices, 1987.
6月号、第63ページに記載のように、溶融状態のはん
だ浴に超音波を付加し、半導体チップを浸漬し、はんだ
バンプを形成する方法があった。As described in the June issue, page 63, there was a method of applying ultrasonic waves to a molten solder bath, immersing a semiconductor chip, and forming solder bumps.
しかし、この方法では一般に形成されるはんだバンプ高
さも10μm程度から数十μm程度と低く、しかもばら
つきが大きいのが問題であった。However, the problem with this method is that the height of the solder bumps that are generally formed is as low as about 10 μm to several tens of μm, and that the variation is large.
すなわち従来方法では、溶融はんだ自体が加熱源を兼ね
、しかも供給量はパッドの大きさに比してほとんど無限
に等しいため、はんだ浴から引き上げる際のわずかな条
件変動により、はんだ量が大きく変化することが避けら
れなかった。In other words, in the conventional method, the molten solder itself also serves as the heating source, and the amount supplied is almost infinite compared to the size of the pad, so slight changes in conditions when pulling the pad out of the solder bath can cause large changes in the amount of solder. It was inevitable.
一方旧来からのこの種のバンプ形成法は、所gの電極位
置にはんだ全マスク蒸着するとか、あるいは湿式のめっ
きをほどこす方式がとられていた。On the other hand, conventional methods for forming bumps of this type have involved depositing solder entirely on a mask at a predetermined electrode position g, or applying wet plating.
これらの方式の大きな欠点は、蒸着では厚いはんだを供
給するのが極めてコスト高となることがあシ、めっき法
では若干コストは下がるものの、エツチング精度との兼
ね合いから、はんだ量の供給精度が下がることや、場合
によってはめっきやエツチング液の液残留による腐食の
問題等があった。The major disadvantage of these methods is that supplying thick solder with vapor deposition can be extremely costly, while with plating, although the cost is slightly lower, the accuracy of supplying the amount of solder decreases due to the need for etching accuracy. In some cases, there were problems with corrosion due to residual plating and etching solutions.
しかもこれらの方法では、AP、電極上へ接着用メタラ
イズを別途形成することが前提であり、この分のコスト
上昇は避けられなかった。Furthermore, these methods require separate formation of adhesive metallization on the AP and electrodes, which inevitably increases costs.
従来技術は、いずれも供給はんだ量の精度や、バンプ形
成コストの点で充分に配慮がなされておらず、汎用技術
としてのバンプ形成法としては採用し難いという問題が
あった。All of the conventional techniques have the problem that sufficient consideration has not been given to the accuracy of the amount of solder supplied and the cost of forming bumps, making it difficult to adopt them as a bump forming method as a general-purpose technique.
本発明の目的は、上記問題点を簡便な方法で解決し、低
コストで精度の良いはんだバンプを形成することにある
。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems using a simple method and to form solder bumps with high precision at low cost.
上記問題点は、コスト面では、高価なAuパンダをはん
だバンプとし、しかも接着用のメタライズを廃してM電
極へ直接はんだ付することで、またはんだの供給鑞制御
については、ドライフィルムを用いた電極部へのはんだ
ペーストの定社供給によシ、任意の高さで、しかも精度
の良いはんだバンプの形成が、達成される。In terms of cost, the above problem can be solved by using expensive Au pandas as solder bumps, eliminating metallization for adhesion and directly soldering to the M electrode, and using dry film to control the solder supply. By supplying solder paste to the electrode parts from a regular company, it is possible to form solder bumps at any desired height and with high precision.
ドライフィルムはウェハ状でラミネートされる。 The dry film is laminated in wafer form.
このため個々のチップ処理では無いため工数増は余りコ
ストに効かない。またエツチングによって形成した電極
部のスルーホールは、エツチング精度が良く、この穴に
はんだペーストを供給すれば高精度のペースト供給が可
能である。Therefore, since individual chips are not processed, increasing the number of man-hours does not have much effect on cost. Further, the through holes in the electrode portion formed by etching have good etching accuracy, and if solder paste is supplied to these holes, paste can be supplied with high precision.
さらに超音波を付加しつつ加熱することで、はんだはM
電極膜上の酸化物層をキャビテーション効果によって破
壊し、Mと金属学的接合を確保しつつ接続する。このと
きペースト材料、超音波付加条件を工夫することで、他
部材へはんだが付着する等の障害は無い。Furthermore, by heating while applying ultrasonic waves, the solder becomes M
The oxide layer on the electrode film is destroyed by the cavitation effect and connected to M while ensuring metallurgical bonding. At this time, by adjusting the paste material and the ultrasonic application conditions, there is no problem such as adhesion of solder to other components.
以上により、M電極上に安価で精度の良い・(ンプ形成
が可能となり、同チップはTAB用あるし・はフリップ
チップ用として使用可能となる。As described above, it is possible to form a chip with high precision at low cost on the M electrode, and the chip can be used for TAB or flip chip.
以下、本発明の一実施例を第1図により説明する0
まず、(α)市販の通常のドライフィルム1(厚さ40
μm)tウェハテップ3上にラミネートし、これも当該
業者が周知の方法にて、(b)電極部に120μm角の
スルーホールを露光・現像して作成した。An embodiment of the present invention will be described below with reference to FIG. 1. First, (α) a commercially available ordinary dry film 1 (thickness:
[mu]m) It was laminated on T wafer step 3, and this was also created by exposing and developing a 120 [mu]m square through hole in the electrode part (b) using a method well known to those skilled in the art.
ついで、(c) 63%Sn−s7%Pb組成のはんだ
にTi r Cd r sb等をm鼠に含む市販はんだ
を10μm径以下0はんだ粉末と[7,ロジンを含む有
機バインダでfM紳し95+#t%はんだの組成とし、
粘度150K Cl) Sのペースト状としたものを、
スクリーン印刷用のゴム脚スキージにて、上記スルーホ
ール中に充てんした。Next, (c) solder with a composition of 63% Sn-s 7% Pb and a commercially available solder containing Ti r Cd r sb etc. were mixed with solder powder of 10 μm or less in diameter and an organic binder containing rosin to form a fM 95+. #t% solder composition,
A paste of viscosity 150K Cl) S is
The above through hole was filled with a rubber leg squeegee for screen printing.
さらに(d)ウェハ上下から約270℃の加熱ツール6
を押し当て、約20KH7の超音波を付加し、接続した
。ペーストはんだは、溶融し、さらに超音波のキャビテ
ーション効果により、M電極上のAl2O5酸化膜を破
壊し、一部金属接合、一部カツブリング効果による接続
にて、はんだバンプが形成される。Furthermore, (d) heating tool 6 at approximately 270°C from above and below the wafer.
, and applied ultrasonic waves of about 20KH7 to connect. The paste solder is melted, and the Al2O5 oxide film on the M electrode is destroyed by the cavitation effect of ultrasonic waves, and a solder bump is formed by partially metal bonding and partially connecting by the cobbling effect.
ツール除去後、(e)ドライフィルムを通常の方法によ
り除去して、高さ55μmのはんだバンプを得た。ドラ
イフィルムは耐熱性の点でツール押当時に、はく離等が
生じろが、本発明に係るバンプ形成につ〜・ては、はん
だがM電極にぬれることにより、影響はなかった。After removing the tool, (e) the dry film was removed by a conventional method to obtain solder bumps with a height of 55 μm. Due to the heat resistance of the dry film, peeling may occur when the tool is pressed, but there was no effect on bump formation according to the present invention because the solder wetted the M electrode.
この後S1ウエハは通常のダイシング工程を経て、TA
Bあるいはフリップテップ等の実装が可能となる。After this, the S1 wafer goes through the normal dicing process and is then TA
It becomes possible to implement B or flip-step.
本発明によれば、A1′r!L極上に接着用メタライズ
を形成する必要はな(、又蒸着、めっき等のプロセスが
不用となる、又、高価なAuバンプをはんだパンダにお
きかえられるので、通常のワイヤボンド用チップに対し
て、わずかなコスト上昇にて、付加価値の高いLSIチ
ップ全製造できる。According to the invention, A1′r! There is no need to form adhesive metallization on the L electrode (also, processes such as vapor deposition and plating are not required), and expensive Au bumps can be replaced with solder pandas, so compared to ordinary wire bond chips, All LSI chips with high added value can be manufactured with a slight increase in cost.
第1図は、本発明の一実施例によるプロセスの大略を、
断面の一部拡大図として示した工程図である。
1・・・ドライフィルム、 2・・・A1’4極膜、
3・・・S1ウエハ(チップ)、4・・・はんだペース
ト、5・・・はんだパンダ、6・・・加熱・超音波付加
ツール。
代理人弁、(± 小 川 勝 F−″躬
l−・ ドライフ本ルー
?・・−A7電ネジll爽
3−・−8iウエハ(+−,ブン
4・−r7fi−r−:イースト
5−・・l;ん六′ハ・〉アFIG. 1 schematically shows a process according to an embodiment of the present invention.
It is a process diagram shown as a partially enlarged view of a cross section. 1... Dry film, 2... A1' quadrupolar film,
3... S1 wafer (chip), 4... Solder paste, 5... Solder panda, 6... Heating/ultrasonic application tool. Proxy valve, (± Masaru Ogawa F-"謬l-・Dry life book Ru?...-A7 electric screw ll So3-・-8i wafer (+-, Bun 4・-r7fi-r-: East 5-・・l;n6′ha・〉a
Claims (1)
をラミネートし、所定のバンプ位置に、所定の形状に穴
をらがち、穴にはんだペーストを充てんし、超音波を付
加しつつはんだを溶融することによって、Al電極上に
直接はんだバンプを形成することを特徴とする半導体装
置の製造方法。1. Laminate a dry film on a wafer that has gone through the normal chip process, make holes in a predetermined shape at predetermined bump positions, fill the holes with solder paste, and melt the solder while applying ultrasonic waves. A method for manufacturing a semiconductor device, comprising forming solder bumps directly on an Al electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24102288A JPH0290529A (en) | 1988-09-28 | 1988-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24102288A JPH0290529A (en) | 1988-09-28 | 1988-09-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0290529A true JPH0290529A (en) | 1990-03-30 |
Family
ID=17068172
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24102288A Pending JPH0290529A (en) | 1988-09-28 | 1988-09-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0290529A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06112212A (en) * | 1992-09-25 | 1994-04-22 | Rohm Co Ltd | Forming method for bump electrode of electronic parts |
JPH06196486A (en) * | 1992-12-14 | 1994-07-15 | Nec Corp | Bump forming method and device |
US6028011A (en) * | 1997-10-13 | 2000-02-22 | Matsushita Electric Industrial Co., Ltd. | Method of forming electric pad of semiconductor device and method of forming solder bump |
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
KR20020026638A (en) * | 2000-10-02 | 2002-04-12 | 듀흐 마리 에스. | A Method of Forming Bumps on Wafers or Substrates |
US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
US20190143726A1 (en) * | 2017-11-10 | 2019-05-16 | Te Connectivity Corporation | Aluminum Based Solderable Contact |
-
1988
- 1988-09-28 JP JP24102288A patent/JPH0290529A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
JPH06112212A (en) * | 1992-09-25 | 1994-04-22 | Rohm Co Ltd | Forming method for bump electrode of electronic parts |
JPH06196486A (en) * | 1992-12-14 | 1994-07-15 | Nec Corp | Bump forming method and device |
US6028011A (en) * | 1997-10-13 | 2000-02-22 | Matsushita Electric Industrial Co., Ltd. | Method of forming electric pad of semiconductor device and method of forming solder bump |
US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
KR20020026638A (en) * | 2000-10-02 | 2002-04-12 | 듀흐 마리 에스. | A Method of Forming Bumps on Wafers or Substrates |
US20190143726A1 (en) * | 2017-11-10 | 2019-05-16 | Te Connectivity Corporation | Aluminum Based Solderable Contact |
US10933675B2 (en) * | 2017-11-10 | 2021-03-02 | Te Connectivity Corporation | Aluminum based solderable contact |
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