JPH08115946A - Flip-chip mounting method - Google Patents
Flip-chip mounting methodInfo
- Publication number
- JPH08115946A JPH08115946A JP6247682A JP24768294A JPH08115946A JP H08115946 A JPH08115946 A JP H08115946A JP 6247682 A JP6247682 A JP 6247682A JP 24768294 A JP24768294 A JP 24768294A JP H08115946 A JPH08115946 A JP H08115946A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metal paste
- solder bump
- jig
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13609—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子のフリップ
チップ実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method for semiconductor devices.
【０００２】[0002]
【従来の技術】近年、半導体実装は高密度化の方向に進
んでおり、実装面積の低減や、電極数の増加に対応する
ためには、フリップチップ実装（ベアチップのフェース
ダウン実装）が有効であると考えられている。2. Description of the Related Art In recent years, semiconductor mounting has been progressing toward higher density, and flip chip mounting (face-down mounting of bare chip) is effective for reducing the mounting area and increasing the number of electrodes. Is believed to be.
【０００３】従来のフリップチップ実装方法は、例えば
特開昭５７−１０６０５７号公報に示されるように、半
導体素子に形成した半田バンプ上に、メッキなどにより
接合材としての半田を析出させた後、半導体素子と基板
とを位置合わせして加熱することにより、接合材として
の半田を溶融させて、基板と半導体素子とを接続するも
のがある。In the conventional flip chip mounting method, for example, as disclosed in Japanese Patent Laid-Open No. 57-106057, after solder as a bonding material is deposited on a solder bump formed on a semiconductor element by plating, There is a method in which a semiconductor element and a substrate are aligned and heated to melt solder as a bonding material to connect the substrate and the semiconductor element.
【０００４】また、特開平３−１３６２５９号公報に示
されるように、半導体素子に形成した半田バンプに対向
する基板の電極（導体）上に、スクリーン印刷法やメタ
ルマスクを用いて金属ペーストを印刷し、半導体素子と
基板とを位置合わせした後、金属ペーストを溶融するこ
とにより基板と接続する方法もある。Further, as disclosed in Japanese Patent Laid-Open No. 3-136259, a metal paste is printed on an electrode (conductor) of a substrate facing a solder bump formed on a semiconductor element by using a screen printing method or a metal mask. Then, after aligning the semiconductor element and the substrate, there is also a method of connecting the substrate by melting the metal paste.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上記従来
の方法では以下のような問題がある。すなわち、前者の
方法では、析出させる半田の組成を常に一定にすること
はかなり困難であるなど、メッキ工程そのものが複雑で
あるため量産性に欠けるのものであった。However, the above-mentioned conventional method has the following problems. That is, in the former method, it is quite difficult to always keep the composition of the deposited solder constant, and the plating process itself is complicated.
【０００６】また後者の方法では、金属ペーストの版抜
けにより、金属ペーストが全く印刷されないときには接
続不良を起こしてしまう。また、金属ペーストを狭ピッ
チで印刷することには限界があり、昨今の狭ピッチ化の
要請には対応できないという問題があった。Further, in the latter method, due to the missing of the metal paste, a connection failure may occur when the metal paste is not printed at all. Further, there is a limit to printing the metal paste at a narrow pitch, and there is a problem that the recent demand for a narrow pitch cannot be met.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
本発明のフリップチップ実装方法は、予め半導体素子に
形成した半田バンプ上に、治具を用いて前記半田バンプ
の融点以下の合金または金属単体を主成分とする金属ペ
ーストを接合材として転写しておき、その後半導体素子
と基板とを位置合わせし、転写した金属ペーストの融点
以上の温度に加熱し、金属ペーストを溶融させることに
より半導体素子と基板とを接合しようとするものであ
る。In order to solve the above-mentioned problems, a flip-chip mounting method of the present invention comprises a solder bump previously formed on a semiconductor element, and an alloy or metal whose melting point is lower than that of the solder bump by using a jig. A metal paste containing a single substance as a main component is transferred as a bonding material, and then the semiconductor element and the substrate are aligned with each other and heated to a temperature equal to or higher than the melting point of the transferred metal paste to melt the metal paste. And the substrate are to be joined together.
【０００８】[0008]
【作用】上記方法によれば、半田バンプ上に接合用金属
を析出させるためのメッキなどの複雑な工程や、基板上
に接合材用金属ペーストを印刷する工程などによらずと
も、半導体素子と基板との接続に必要な金属ペースト
を、半田バンプ上に得ることができる。According to the above method, a semiconductor element can be formed without depending on complicated steps such as plating for depositing the joining metal on the solder bumps and the step of printing the joining material metal paste on the substrate. The metal paste required for connection with the substrate can be obtained on the solder bumps.
【０００９】[0009]
【実施例】以下、本発明のフリップチップ実装方法につ
いて、その実施例を図面を参照しながら具体的に説明す
る。図１は本発明の第１の実施例を示すものであり、実
装工程の順に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The flip chip mounting method of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of the present invention, which will be described in the order of mounting steps.
【００１０】予め半導体素子の電極上に、メッキや転写
方法（例えば特開平４−２６３４３３号公報）などの公
知の方法で半田バンプを形成しておく（図示せず）。図
（ａ）において、上面が平らな治具３上に、無秩序に金
属ペースト２を盛る。そして図（ｂ）に示すように、ス
キージ１を治具３と一定の隙間をあけて摺動させること
により、金属ペースト２を薄く均一に塗る（図
（ｃ））。Solder bumps are previously formed on the electrodes of the semiconductor element by a known method such as plating or a transfer method (for example, Japanese Patent Laid-Open No. 4-263433) (not shown). In FIG. 3A, the metal paste 2 is randomly deposited on the jig 3 having a flat upper surface. Then, as shown in FIG. 2B, the squeegee 1 is slid on the jig 3 with a constant gap therebetween to apply the metal paste 2 thinly and uniformly (FIG. 1C).
【００１１】治具３としては、表面が研磨されたステン
レス、ガラス、アルミニウムあるいはセラミックスなど
を使用し、金属ペースト２としては、半田バンプの融点
以下の合金または金属単体を主成分とする金属ペースト
を用い、例えばフラックスを９ｗｔ％含有し、半田粒の
粒径が１０〜３０μｍであり、その組成が６３ｗｔ％Ｓ
ｎ−３７ｗｔ％Ｐｂであるものを用いることができる。The jig 3 is made of stainless steel, glass, aluminum or ceramics having a polished surface, and the metal paste 2 is an alloy having a melting point of the solder bump or lower or a metal paste containing a simple metal as a main component. For example, containing 9 wt% of flux, the grain size of the solder particles is 10 to 30 μm, and the composition thereof is 63 wt% S
It is possible to use one that is n-37 wt% Pb.
【００１２】次に図（ｄ）に示すように、前記半導体素
子４に形成した半田バンプ５を下向きにして治具３に載
置した後、半導体素子４を治具３から引き離し、図
（ｅ）に示すように、半導体素子４の半田バンプ５上
に、金属ペースト２を転写する。これは金属ペースト中
に含まれているフラックスの粘性により、金属ペースト
２が半田バンプ５上に粘着するのである。そして図
（ｆ）に示すように、金属ペースト２が転写された半導
体素子４を基板６上の電極（導体）７に位置合わせし、
この状態でリフロー処理を行い、半田バンプ５の融点よ
り低い温度で金属ペースト２を溶融させることにより、
半導体素子４と基板６とを接合する。Next, as shown in FIG. 3D, after the solder bumps 5 formed on the semiconductor element 4 are placed on the jig 3 with the solder bumps 5 facing downward, the semiconductor element 4 is separated from the jig 3, and the step shown in FIG. ), The metal paste 2 is transferred onto the solder bumps 5 of the semiconductor element 4. This is because the viscosity of the flux contained in the metal paste causes the metal paste 2 to adhere to the solder bumps 5. Then, as shown in FIG. 6F, the semiconductor element 4 on which the metal paste 2 is transferred is aligned with the electrode (conductor) 7 on the substrate 6,
By performing a reflow process in this state and melting the metal paste 2 at a temperature lower than the melting point of the solder bump 5,
The semiconductor element 4 and the substrate 6 are bonded together.
【００１３】次に本発明の第２の実施例を図面を用いて
詳細に説明する。上記第１の実施例と異なるのは、治具
３としてカーボンの焼結体、ガラスあるいはステンレス
を用い、その表面にドリル加工あるいはエッチングによ
り、半導体素子４の半田バンプ５と同じピッチで凹部８
を形成した点であり、以下その実装工程を説明する。Next, a second embodiment of the present invention will be described in detail with reference to the drawings. The difference from the first embodiment is that the jig 3 is made of a carbon sintered body, glass or stainless steel, and the surface thereof is drilled or etched to form recesses 8 at the same pitch as the solder bumps 5 of the semiconductor element 4.
That is, the mounting process will be described below.
【００１４】治具３の凹部８に、スキージ１を用いて前
記半田バンプ５の融点以下の合金または金属単体を主成
分とする金属ペースト２を充填する。次に図（ｃ）のよ
うに半田バンプ５の形成面を下向きにして治具３と半導
体素子４を整合し、その後半導体素子４を治具３から引
き離すことにより、図（ｄ）のように半導体素子４の半
田バンプ５上に金属ペースト２を転写する。そして図
（ｅ）のように、基板６上の電極（導体）７と位置合わ
せし、この状態でリフロー処理を行い、半田バンプ５の
融点より低い温度で、金属ペースト２を溶融させること
により、半導体素子４と基板６とを接合する。The squeegee 1 is used to fill the concave portion 8 of the jig 3 with the metal paste 2 whose main component is an alloy having a melting point of the solder bump 5 or less, or a simple metal. Next, as shown in FIG. 3C, the jig 3 and the semiconductor element 4 are aligned so that the surface on which the solder bumps 5 are formed faces downward, and then the semiconductor element 4 is separated from the jig 3 so that as shown in FIG. The metal paste 2 is transferred onto the solder bumps 5 of the semiconductor element 4. Then, as shown in FIG. 6E, the metal paste 2 is aligned with the electrodes (conductors) 7 on the substrate 6, reflow treatment is performed in this state, and the metal paste 2 is melted at a temperature lower than the melting point of the solder bumps 5. The semiconductor element 4 and the substrate 6 are bonded together.
【００１５】この実施例によると、半導体素子４の半田
バンプ５と同じピッチで形成した凹部８内に金属ペース
ト２を充填しているので、治具３から半導体素子４へ金
属ペースト２を転写する際に、隣接する半田バンプ５間
で金属ペースト２がブリッジをおこす可能性は皆無とな
り、狭ピッチ化に有効な方法であるといえる。According to this embodiment, since the metal paste 2 is filled in the recesses 8 formed at the same pitch as the solder bumps 5 of the semiconductor element 4, the metal paste 2 is transferred from the jig 3 to the semiconductor element 4. At this time, there is no possibility that the metal paste 2 will cause a bridge between the adjacent solder bumps 5, and it can be said that this is an effective method for narrowing the pitch.
【００１６】さらに、上記第１の実施例では、治具３に
塗布する金属ペースト２の厚さを、治具３と半導体素子
４の本体との間隔より薄くし、半導体素子４に金属ペー
スト２が付着しないようにする必要があるが、本実施例
ではそのような必要はなく作業性の良いものとなる。Further, in the first embodiment, the thickness of the metal paste 2 applied to the jig 3 is made smaller than the distance between the jig 3 and the main body of the semiconductor element 4, and the metal paste 2 is applied to the semiconductor element 4. However, in the present embodiment, there is no such need and workability is improved.
【００１７】なお上記第１及び第２の実施例において、
金属ペースト２のフラックス含有率は、作業性および転
写量を考慮して決定すれば良く、上記含有率に限定され
ない。またその組成についても、錫（Ｓｎ）、鉛（Ｐ
ｂ）、ビスマス（Ｂｉ）、インジウム（Ｉｎ）を主とす
る合金または単体でも良い。また金属ペースト２の半田
粒の粒径は、第１の実施例では半田バンプ５の大きさ以
下であれば良く、第２の実施例では半田バンプ５のピッ
チ以下、すなわち治具３上の凹部の径以下であれば良
い。さらに、基板６としてはセラミック基板はもちろん
のことガラスエポキシ基板に代表される有機樹脂基板や
フレキシブルプリント基板などにも応用できる。In the above first and second embodiments,
The flux content of the metal paste 2 may be determined in consideration of workability and transfer amount, and is not limited to the above content. Regarding the composition, tin (Sn), lead (Pn
An alloy containing b), bismuth (Bi), indium (In) or a simple substance may be used. Further, the particle size of the solder particles of the metal paste 2 may be equal to or smaller than the size of the solder bump 5 in the first embodiment, and may be equal to or smaller than the pitch of the solder bump 5 in the second embodiment, that is, the concave portion on the jig 3. It is sufficient if it is less than or equal to the diameter. Further, the substrate 6 can be applied not only to a ceramic substrate but also to an organic resin substrate represented by a glass epoxy substrate, a flexible printed circuit board, or the like.
【００１８】[0018]
【発明の効果】以上のように本発明のフリップチップ実
装方法によれば、量産に優れ低コストで信頼性の高いフ
リップチップ実装が実現できる。また今後要求が高まっ
てくる半導体素子上の電極の狭ピッチ化にも十分対応す
ることができる。As described above, according to the flip-chip mounting method of the present invention, it is possible to realize flip-chip mounting which is excellent in mass production, low in cost, and high in reliability. Further, it is possible to sufficiently cope with the narrowing of the pitch of electrodes on a semiconductor element, which is required in the future.
【図１】本発明の第１の実施例を示す実装工程図FIG. 1 is a mounting process diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す実装工程図FIG. 2 is a mounting process diagram showing a second embodiment of the present invention.
１ スキージ ２ 金属ペースト ３ 治具 ４ 半導体素子 ５ 半田バンプ ６ 基板 ７ 電極（導体） ８ 凹部 1 Squeegee 2 Metal Paste 3 Jig 4 Semiconductor Element 5 Solder Bump 6 Substrate 7 Electrode (Conductor) 8 Recess
Claims (2)
が平らな治具とが対向するように載置した場合に、前記
半導体素子本体と治具との間に形成される間隔よりも薄
い厚さで、前記半田バンプよりも低い融点の金属ペース
トを前記治具上に塗布する工程と、 前記金属ペーストを塗布した治具上に、前記半導体素子
の半田バンプ形成面を対向させて載置し、その後、前記
半導体素子を取り外して、前記半田バンプの表面に前記
金属ペーストを転写する工程と、 前記金属ペーストが転写された半導体素子を基板上に載
置し、前記半田バンプの融点よりも低い温度にて、前記
金属ペーストを加熱、溶融することにより、半導体素子
と基板とを接続する工程とを備えたフリップチップ実装
方法。1. When a solder bump formed on a semiconductor element and a jig having a flat upper surface are placed so as to face each other, the thickness is thinner than a space formed between the semiconductor element body and the jig. Now, a step of applying a metal paste having a melting point lower than that of the solder bump on the jig, and placing the solder bump forming surface of the semiconductor element on the jig on which the metal paste is applied so as to face each other. After that, the step of removing the semiconductor element and transferring the metal paste onto the surface of the solder bump, and placing the semiconductor element on which the metal paste is transferred on a substrate, and lower than the melting point of the solder bump A flip chip mounting method comprising a step of connecting a semiconductor element and a substrate by heating and melting the metal paste at a temperature.
り融点が低い金属ペーストを、前記半田バンプと対向す
るように治具の表面に形成した凹部に充填する工程と、 前記金属ペーストを充填した治具の凹部に、前記半導体
素子の半田バンプを対向させて載置し、その後、前記半
導体素子を取り外して、前記半田バンプの表面に前記金
属ペーストを転写する工程と、 前記金属ペーストが転写された半導体素子を基板上に載
置し、前記半田バンプよりも低い温度にて、前記金属ペ
ーストを加熱、溶融することにより、半導体素子と基板
とを接続する工程とを備えたフリップチップ実装方法。2. A step of filling a metal paste having a melting point lower than that of a solder bump previously formed on a semiconductor element into a concave portion formed on the surface of the jig so as to face the solder bump, and a method of filling the metal paste with a metal paste. A step of placing the solder bumps of the semiconductor element so as to face each other in the concave portion of the tool, then removing the semiconductor element, and transferring the metal paste to the surface of the solder bump, and the metal paste being transferred A flip-chip mounting method comprising: mounting a semiconductor element on a substrate; and heating and melting the metal paste at a temperature lower than that of the solder bump to connect the semiconductor element and the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6247682A JPH08115946A (en) | 1994-10-13 | 1994-10-13 | Flip-chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6247682A JPH08115946A (en) | 1994-10-13 | 1994-10-13 | Flip-chip mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08115946A true JPH08115946A (en) | 1996-05-07 |
Family
ID=17167087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6247682A Pending JPH08115946A (en) | 1994-10-13 | 1994-10-13 | Flip-chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08115946A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002071489A1 (en) * | 2001-03-01 | 2002-09-12 | Mitsubishi Heavy Industries, Ltd. | Image sensor and production method therefore |
| WO2003041175A1 (en) * | 2001-11-05 | 2003-05-15 | Mitsubishi Heavy Industries, Ltd. | Image sensor and its manufacturing method |
| KR100722058B1 (en) * | 1997-08-08 | 2007-08-16 | 마쯔시다덴기산교 가부시키가이샤 | Apparatus for the mount of small balls |
-
1994
- 1994-10-13 JP JP6247682A patent/JPH08115946A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100722058B1 (en) * | 1997-08-08 | 2007-08-16 | 마쯔시다덴기산교 가부시키가이샤 | Apparatus for the mount of small balls |
| WO2002071489A1 (en) * | 2001-03-01 | 2002-09-12 | Mitsubishi Heavy Industries, Ltd. | Image sensor and production method therefore |
| EP1365453A1 (en) * | 2001-03-01 | 2003-11-26 | Mitsubishi Heavy Industries, Ltd. | Image sensor and production method therefore |
| US6992297B2 (en) | 2001-03-01 | 2006-01-31 | Mitsubishi Heavy Industries Ltd. | Image sensor and manufacturing method thereof |
| US7041981B2 (en) | 2001-03-01 | 2006-05-09 | Mitsubishi Heavy Industries Ltd. | Image sensor and manufacturing method thereof |
| EP1365453A4 (en) * | 2001-03-01 | 2008-04-30 | Mitsubishi Heavy Ind Ltd | Image sensor and production method therefore |
| WO2003041175A1 (en) * | 2001-11-05 | 2003-05-15 | Mitsubishi Heavy Industries, Ltd. | Image sensor and its manufacturing method |
| US7042008B2 (en) | 2001-11-05 | 2006-05-09 | Mitsubishi Heavy Industries, Ltd. | Image sensor and method of manufacturing the same |
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