JPH0218584B2 - - Google Patents
Info
- Publication number
- JPH0218584B2 JPH0218584B2 JP18586481A JP18586481A JPH0218584B2 JP H0218584 B2 JPH0218584 B2 JP H0218584B2 JP 18586481 A JP18586481 A JP 18586481A JP 18586481 A JP18586481 A JP 18586481A JP H0218584 B2 JPH0218584 B2 JP H0218584B2
- Authority
- JP
- Japan
- Prior art keywords
- solder layer
- solder
- semiconductor wafer
- back electrode
- suction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000679 solder Inorganic materials 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000008188 pellet Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】
この発明は、裏面電極上に半田層を形成した半
導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which a solder layer is formed on a back electrode.
半導体ペレツトをろう付けによつてステムやリ
ードフレームにマウントする場合、溶融半田上に
ペレツトを押し付ける方法では、溶融半田表面に
酸化やフラツクスの浮き出しによる表面膜が形成
されて接着を阻害するので、これを破壊するため
の操作が必要となつて生産性が悪化する。そこ
で、ペレツトの裏面電極上に予め半田層を形成し
ておき、これをマウント面に当接した状態で半田
層を加熱溶融してマウントするペレツト予備半田
法と称される方法が考えられている。 When mounting semiconductor pellets on a stem or lead frame by brazing, pressing the pellets onto molten solder will create a surface film on the surface of the molten solder due to oxidation or embossed flux, which will inhibit adhesion. Productivity deteriorates as operations are required to destroy the Therefore, a method called the pellet pre-soldering method has been considered, in which a solder layer is formed in advance on the back electrode of the pellet, and the solder layer is heated and melted while the solder layer is in contact with the mounting surface and mounted. .
ところが、このようなペレツトを得るために分
離前の半導体ウエーハに半田層を形成すると、半
田層が軟らかく且つ比較的厚みを有することに起
因して、半導体ウエーハを格子状に区割してペレ
ツトに分離するとき、切断用のダイシングプレー
ドに目詰まりを生じて切断が困難となり易く、ま
た半導体ウエーハの表面側から区割線に沿つて途
中まで溝を形成して破断する方法でも半田層部で
破断面が不揃いとなつていわゆるアベツク不良を
生じ易い。一方、これを解決するために半導体ウ
エーハの区割すべき分割線に沿つて半田層の存在
しない部分を形成する方法が提案されているが、
この方法は裏面電極のオーミツク金属と半導体の
例えばシリコンとの半田に対する漏れ性の差を利
用してシリコン部に溶融半田が付着しないように
するものであるため、オーミツク金属を非常に工
数の多い写真蝕刻法で格子状にエツチング除去し
てパターン化する必要があり、時間的な損失が大
きく、材料面からもコスト高となる。 However, when a solder layer is formed on a semiconductor wafer before separation in order to obtain such pellets, the solder layer is soft and relatively thick, so it is necessary to divide the semiconductor wafer into a lattice pattern and form it into pellets. When separating, the dicing blade used for cutting tends to become clogged, making cutting difficult.Also, even with a method in which grooves are formed partway from the front side of the semiconductor wafer along the parting line and the wafer is broken, the dicing blade for cutting tends to become clogged. This tends to cause so-called average defects due to unevenness. On the other hand, in order to solve this problem, a method has been proposed in which a portion where no solder layer exists is formed along the dividing line of the semiconductor wafer.
This method takes advantage of the difference in solder leakage between the ohmic metal of the back electrode and the semiconductor, such as silicon, to prevent molten solder from adhering to the silicon part. It is necessary to remove the pattern by etching it in a lattice shape using an etching method, which results in a large loss of time and increases costs in terms of materials.
この発明は、上記従来の欠点を改善することを
目的としており、半導体ウエーハの裏面電極側の
全面に所定厚みの半田層を形成した後、ペレツト
に区割する格子状パターンに沿つて半田層を溶融
させると共に、この溶融した半田を吸引除去する
ことにより、格子状に裏面電極を露出させ、この
後上記露出した裏面電極から半導体ウエーハを切
断してペレツトに分離することを特徴とする半導
体装置の製造方法に係る。 This invention aims to improve the above-mentioned conventional drawbacks, and after forming a solder layer of a predetermined thickness on the entire surface of the back electrode side of a semiconductor wafer, the solder layer is spread along a lattice pattern divided into pellets. A semiconductor device characterized in that a back electrode is exposed in a grid pattern by melting and removing the molten solder by suction, and then the semiconductor wafer is cut from the exposed back electrode and separated into pellets. Regarding the manufacturing method.
以下、この発明の方法を図面によつて説明すれ
ば、まず、第１図で示すように半導体ウエーハ１
の裏面側のオーミツク金属層からなる裏面電極２
の表面に、所定厚みで半田層３を形成する。図中
４は区割すべきペレツト単位を示し、このペレツ
ト単位４はそれぞれ目的とする半導体素子単位を
含んでおり、またペレツト単位４の区割線５は格
子状パターンとなつている。次に、上記半田層３
を区割線５に沿つて所定幅で溶融させ、直後に溶
融半田を吸引除去し、第２図で示すように表面電
極２表面を格子状に露出させる。その後、上記格
子状パターンの露出した裏面電極から常法に準じ
て切断し、第３図で示すようなペレツト単位４に
分離する。 Below, the method of the present invention will be explained with reference to the drawings. First, as shown in FIG. 1, a semiconductor wafer 1 is
Back electrode 2 consisting of an ohmic metal layer on the back side of
A solder layer 3 is formed with a predetermined thickness on the surface. In the figure, numeral 4 indicates pellet units to be divided, each of which contains a target semiconductor element unit, and the dividing lines 5 of the pellet units 4 form a lattice pattern. Next, the solder layer 3
The solder is melted in a predetermined width along the dividing line 5, and the molten solder is immediately removed by suction to expose the surface of the surface electrode 2 in a grid pattern as shown in FIG. Thereafter, the exposed back electrode of the lattice pattern is cut according to a conventional method to separate into pellet units 4 as shown in FIG.
上述のように半田層３を格子状パターンで溶融
除去する手段は種々存在するが、特に溶融手段と
吸引除去手段とが一体化された装置の使用が好適
であり、以下その実施例を図面に従つて説明す
る。 As mentioned above, there are various means for melting and removing the solder layer 3 in a lattice pattern, but it is particularly preferable to use a device in which a melting means and a suction removal means are integrated. I will explain accordingly.
第４図は半田層３の溶融にレーザ光を利用する
例である。図において、６はレーザ発生装置（図
示略）のレーザ光照射口であり、７は半田層３上
で所定幅となるように焦つたレーザ光を示す。こ
のレーザ光照射口６先端には透明な石英またはガ
ラスで形成された略円錐形の吸引管８が装着され
ている。この吸引管８は枝管８ａでドレーンタン
ク付きの吸引ポンプ（図示略）とチユーブ９を介
して連絡しており、また先端のレーザ光７の照準
に一致する位置に半田吸引口８ｂを備えている。
この装置を使用する場合、レーザ光７の照準点が
半導体ウエーハ１の格子状パターンの区割線５に
沿うようにレーザ発生装置側もしくは半導体ウエ
ーハ１を載せたインデツクステーブル（図示略）
を移動させ、半田層３をレーザ光７で溶融させつ
つ半田吸引口８ｂより溶融半田を吸引除去する。 FIG. 4 shows an example in which laser light is used to melt the solder layer 3. In the figure, 6 is a laser beam irradiation port of a laser generator (not shown), and 7 is a laser beam that has been focused on the solder layer 3 to have a predetermined width. A substantially conical suction tube 8 made of transparent quartz or glass is attached to the tip of the laser beam irradiation port 6 . This suction pipe 8 is connected to a suction pump with a drain tank (not shown) via a tube 9 through a branch pipe 8a, and is provided with a solder suction port 8b at a position corresponding to the aim of the laser beam 7 at the tip. There is.
When using this device, place the laser beam 7 on the laser generator side or on an index table (not shown) on which the semiconductor wafer 1 is placed so that the aiming point of the laser beam 7 is along the division lines 5 of the grid pattern of the semiconductor wafer 1.
is moved, and while the solder layer 3 is melted by the laser beam 7, the molten solder is removed by suction from the solder suction port 8b.
第５図で示す実施例は、半田層３の溶融にヒー
タを利用するものである。第５図において、１０
は先端１０ａが尖つた形状を有する半田ごて形ヒ
ータであり、先端１０ａに開口１０ｂを備え、先
端１０ａとの接触で生じた溶融半田を開口１０ｂ
からヒータ１０内部に設けられた通路１０ｃとこ
れに連結するチユーブ１１を通して吸引除去する
ように構成されている。溶融点の移動は、前記例
と同様にヒータ１０もしくは半導体ウエーハ１の
ステージ（図示略）を動作して行なう。 The embodiment shown in FIG. 5 uses a heater to melt the solder layer 3. In Figure 5, 10
is a soldering iron type heater having a pointed tip 10a, and has an opening 10b at the tip 10a, and the molten solder generated by contact with the tip 10a is passed through the opening 10b.
It is configured to suction and remove the liquid through a passage 10c provided inside the heater 10 and a tube 11 connected thereto. The melting point is moved by operating the heater 10 or the stage (not shown) of the semiconductor wafer 1, as in the previous example.
第６図で示す実施例は、第５図の例と同様にヒ
ータを利用するものであるが、ヒータ１２は格子
状パターンの区割線５の／ラインに相当する部分
の半田層３を一時に溶融するように横長の先端１
２ａを有しており、溶融半田は同様に先端１２ａ
に形成されたスリツト状開口１２ｂより内部の通
路１２ｃとチユーブ１３を通して吸引除去され
る。 The embodiment shown in FIG. 6 uses a heater as in the example shown in FIG. Horizontally long tip 1 to melt
2a, and the molten solder is similarly applied to the tip 12a.
The liquid is removed by suction through the internal passage 12c and the tube 13 through the slit-like opening 12b formed in the slit-like opening 12b.
なお、この発明において、溶融除去する半田層
３の幅は半導体装置の設計によつて決まるが、通
常50〜500μの範囲である。 In the present invention, the width of the solder layer 3 to be melted and removed is determined by the design of the semiconductor device, but is usually in the range of 50 to 500 microns.
以上のように、この発明の方法によれば、半導
体ウエーハの裏面電極側に形成した半田層をペレ
ツトに区割する格子状パターンに沿つて極めて容
易に除去できるため、半導体ウエーハをペレツト
に分離する際、ダイシングプレートに目詰まりを
生じたり、破断でアベツク不良を生じることがな
く、分離が非常に容易となり、その結果として裏
面に半田層を形成した半導体装置を容易かつ安価
に提供できる。 As described above, according to the method of the present invention, the solder layer formed on the back electrode side of the semiconductor wafer can be removed very easily along the grid pattern that divides the semiconductor wafer into pellets. At this time, the dicing plate does not become clogged or the average defect occurs due to breakage, and separation becomes very easy. As a result, a semiconductor device having a solder layer formed on the back surface can be provided easily and at low cost.
第１図乃至第３図はこの発明の半導体装置の製
造方法を工程順に示し、第１図は裏面全面に半田
層を形成した半導体ウエーハの断面図、第２図は
区割線に沿つて半田層を溶融除去した半導体ウエ
ーハの断面図、第３図は半導体ウエーハより分離
したペレツトの断面図であり、第４図乃至第６図
はいずれもこの発明の実施例における半田層の溶
融除去工程を示す斜視図である。
１……半導体ウエーハ、２……裏面電極、３…
…半田層、４……ペレツト単位、５……格子状パ
ターンの区割線。
1 to 3 show the manufacturing method of a semiconductor device according to the present invention in the order of steps. FIG. 1 is a cross-sectional view of a semiconductor wafer with a solder layer formed on the entire back surface, and FIG. FIG. 3 is a cross-sectional view of a pellet separated from the semiconductor wafer, and FIGS. 4 to 6 all show the process of melting and removing the solder layer in an embodiment of the present invention. FIG. 1... Semiconductor wafer, 2... Back electrode, 3...
...Solder layer, 4...Pellet unit, 5...Separator line of grid pattern.
Claims (1)
電極側の全面に所定厚みの半田層を形成した後、
ペレツトに区割する格子状パターンに沿つて半田
層を所定幅で溶融させると共に、この溶融した半
田を吸引除去して格子状に裏面電極面を露出さ
せ、この後上記露出した裏面電極面から半導体ウ
エーハを切断してペレツトに分離することを特徴
とする半導体装置の製造方法。1 After forming a solder layer of a predetermined thickness on the entire surface of the back electrode side of the semiconductor wafer on which a large number of elements have been formed,
The solder layer is melted in a predetermined width along the lattice pattern divided into pellets, and the molten solder is removed by suction to expose the back electrode surface in a lattice pattern. A method for manufacturing a semiconductor device, which comprises cutting a wafer and separating it into pellets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185864A JPS5886743A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185864A JPS5886743A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5886743A JPS5886743A (en) | 1983-05-24 |
| JPH0218584B2 true JPH0218584B2 (en) | 1990-04-26 |
Family
ID=16178212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56185864A Granted JPS5886743A (en) | 1981-11-18 | 1981-11-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5886743A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100514099B1 (en) * | 1998-12-04 | 2005-11-25 | 삼성전자주식회사 | Laser cutting device and cutting method |
| KR100543368B1 (en) * | 1998-12-04 | 2006-05-12 | 삼성전자주식회사 | Laser cutting equipment |
| JP5312970B2 (en) * | 2009-02-06 | 2013-10-09 | 株式会社ディスコ | Semiconductor wafer dividing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017176A (en) * | 1973-06-12 | 1975-02-22 |
-
1981
- 1981-11-18 JP JP56185864A patent/JPS5886743A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017176A (en) * | 1973-06-12 | 1975-02-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5886743A (en) | 1983-05-24 |
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