JPS5817636A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5817636A JPS5817636A JP56115900A JP11590081A JPS5817636A JP S5817636 A JPS5817636 A JP S5817636A JP 56115900 A JP56115900 A JP 56115900A JP 11590081 A JP11590081 A JP 11590081A JP S5817636 A JPS5817636 A JP S5817636A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- solder
- solder layer
- grooves
- lattice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、裏Ｉ！ＩＩ電極に半田層を有する半導体装
置の製造方法に関するものである。[Detailed Description of the Invention] This invention is based on Ura I! The present invention relates to a method of manufacturing a semiconductor device having a solder layer on a II electrode.
墓−電極に半田層を有するタイプの半導体装置を得よう
とする場合、予め半導体ウェーハ（以下単にウェーハと
称する）の−面電極の全面に半田層を形成しておくと、
これを多数の１−々の素子に分離するのは容易でない・
何処なら、これ等の素子をウェーハよ砂分履するため、
薄い砥石等を用いてウェーへの表面側に各素子を区割す
る格子状の溝を形成するが、このとき予め、ウェーハの
長面電極上全面に半田層を形成しておくと、半田層は軟
らかく粘いのと、表面電惚に比べ相幽に厚いため、砥石
等が目詰りし、半田層−より格子状の溝を形成するの＃
′ｉ容易でない。When trying to obtain a type of semiconductor device having a solder layer on the grave electrode, if a solder layer is formed in advance on the entire surface of the minus electrode of a semiconductor wafer (hereinafter simply referred to as a wafer),
It is not easy to separate this into many individual elements.
Wherever, in order to separate these elements from wafers,
Grid-like grooves dividing each element are formed on the surface side of the wafer using a thin grindstone, etc. At this time, if a solder layer is formed on the entire surface of the long electrode of the wafer in advance, the solder layer Because it is soft and sticky and much thicker than surface electromagnetism, it can clog grindstones and form grid-like grooves in the solder layer.
'iIt's not easy.
従って、この楓の半導体装置を製造する一合、１−々の
素子に分離してから半田ｊ−を形成せねばならず、非富
に工数がかかりコストが高くつく。Therefore, when manufacturing this Kaede semiconductor device, it is necessary to separate each element and then form solder, which requires a lot of man-hours and increases costs.
この発明Ｉｒｉ千尋体装置全孤造する悪程に於いて生ず
る上述した間聴点を解決するため、予めウェーハの裏面
電極側より素子を区割する格子状の纏をａ面電極より深
く開設してウェーハのシリコン面を露出させ、この格子
状の溝ＫＭまる浴−半田の滴れ性を悪ろくしておき、ウ
ェーハのＩｋＩｉの全域に溶融半田層を形成した時、上
記溶＃１ｄｌ＃−田をウェーハの区割された各裏面電極
上に＠収させると共に、格子状の溝を露出させ、この後
この格子状の溝１１ｒ：浴ってウェーハを切断して菓子
を分離するようＫした半導体装置の製造方法であって、
以下この尭明の＊１例を図に従って説明すると次の通シ
である・
第７図はシリコン板で形成したウェーハ１１１の断自を
示し、図中１２１ ＃：ｉクエーハ（１）の表面側に縮
短の整列パターンに従って多数形成した素子で、不純物
を拡散させた領域からなっている。（３）は上記ウェー
ハロ）の表面の全域に形成した裏面電極で、以上までの
成形過１！會従来通りの手職に値って行なう・
そして、この半導体装置の製造方法において、以降の成
形ｉ！４根を次の通りに構成する。In order to solve the above-mentioned interacoustic points that occur when the Iri chihiro body device of this invention is completely isolated, a grid-like mesh that divides the elements from the back electrode side of the wafer is opened deeper than the a-side electrode in advance. When the silicon surface of the wafer is exposed and the lattice-shaped grooves KM are made to have poor dripping properties of the solder, when a molten solder layer is formed over the entire area of IkIi of the wafer, the is placed on each divided back electrode of the wafer, and a lattice-shaped groove is exposed. A method for manufacturing a device, the method comprising:
Below, an example of *1 of this method will be explained according to the drawings. Figure 7 shows the cutting of the wafer 111 formed of a silicon plate, and in the figure 121 #: the front side of the i-quafer (1). A large number of elements are formed according to a shortened alignment pattern, and are made up of regions in which impurities are diffused. (3) is the back electrode formed on the entire surface of the wafer (above), and the molding process up to the above is 1! In this semiconductor device manufacturing method, the subsequent molding i! Construct the four roots as follows.
先ず、第２図に示すように、ウェーハｉｌｌの裏面１を
極（３１匈に前記素子（２）を区割する格子状の溝（４
，を薄い砥石を用いて、或いｒｔ′４．真蝕刻によりて
裏面電極１！＋よ）深く開設し、シリコン面を裏面電極
１３）よシ箇出させる。上記格子状の＠１ｃＦｉ谷素子
１！ｌを区割するため、裏面電極（８）上の位置に正確
に開設せねばならず、このため、例えば予めウェーハ（
１）の榎数個所に表ｔｈ側からレザーマーキングによっ
て４投した貞通孔：ＩＳ＋ｙ利用し、表面側の素子１！
）の整列パターンに対応させながらＳ設する。First, as shown in FIG. 2, a lattice-like groove (4
, using a thin grindstone, or rt'4. Back electrode 1 with true etching! ＋) deeply and expose the silicon surface to the back electrode 13). The above lattice @1cFi valley element 1! In order to divide the wafer (
1) Sadamichi hole where 4 pitches were made by laser marking from the obverse th side to several places on the Enoki: Using IS + y, element 1 on the obverse side!
) while corresponding to the alignment pattern.
以上の様Ｋ ４１％ ｔｈｉ［（血ｃｌｌの全域に半田
層を形成する前に格子状の酵１４：を開設しておくと、
後述するように砥石に目詰シが起ることがない。As above, K 41% th
As will be described later, clogging of the grindstone does not occur.
そして、次の成形過程で上記ウェーハ１１１の良圓に半
田層を形成するが、これには早出ペーストを道布する方
法と、＃融牛田を直接供給する、あるいは半田層を真空
蒸着法により堆積させる方法があるのでその両者につい
て説明する。Then, in the next molding process, a solder layer is formed on the surface of the wafer 111, which can be done by distributing a quick release paste, by directly supplying a melting paste, or by depositing a solder layer by vacuum evaporation. There are ways to do this, so I will explain both of them.
第３図は半田ペーストを塗布して溶融半田層１６１を形
成する方法を示す。半田ペーストは粉末状の半田と溶剤
を混ぜ合せたもので、ペースト状を呈し、仁の場合この
半田ペーストをシルクスクリーン法静によってウェーハ
１１１のＭ面の全域に均一の厚さに塗布する。そして、
このままウェーハ１１＋ １−所定の一度に加熱し半田
ペーストを浴融する・溶−の初期段階では、格子状の−
１４１に埋った半田ペーストはそのｔま餅融半田（７）
として残り、上記＠１４：で区割された１面電極１８１
上の１１１融半田層１８）と合せてウェーハロ）の真向
の全域ＫｊＬつた＃融半田層（６）を形成する・第Ｖ図
及び第５図は溶融半田を加熱状態のウェーハロ）の裏面
上Ｋ［接供給して舒融半由層（６ａ）を形成す為方法を
示す、この方法は、Ｍｇガス轡の中性若しくは水素ガス
等の還元性ガスを半田の融点以上に加熱することにより
、あるいは真空吸着台ｍそのものにヒータを内蔵するこ
と勢によって、半田の融点以上に加熱された真空吸着台
ｉＬ上にｘｍｉｓを上向きにウェーハ１１１をチャツタ
し、真空吸着台（９：を回転してこのウェーハｉｌｌに
所足の回転速度を４えると共に、中心位置の上方より陪
畝半田９０・を部下させ、遠心方によってウェーハｉｌ
ｌ上に浴融半田ααを広がらせて所定の厚さの＃融半田
層（６ａ）を形成するものである。場合によっては、ウ
ェーハ（１）を浴融半田中に浸漬したり、真空蒸着法で
形成してもよい。真空蒸着法にょシ半田層１ｍ積させる
方法は、例えは／ｆ”〜／グ４テｏｒｒの真空状態にし
たチャンバーの中にウェハをプラ、ネタリウムに並ヘテ
保持し、所望の半田インゴットｔｐン／ステンコイルよ
り成るルツボを抵抗加熱して蒸竜破着させる方法が利用
できる。また水冷されたルツボ中Ｖｃｔａｒ協の半田イ
ンゴットをセットし、電子線を集中させて加熱する電子
銃弐蒸発被着法によりてもよい。FIG. 3 shows a method of applying solder paste to form a molten solder layer 161. The solder paste is a mixture of powdered solder and a solvent, and is in the form of a paste, and in the case of soldering, this solder paste is applied to the entire M side of the wafer 111 to a uniform thickness by a silk screen method. and,
As it is, the wafer 11+ 1- is heated at a predetermined time to melt the solder paste.In the initial stage of melting, a lattice-shaped -
The solder paste buried in 141 is tmamochi melted solder (7)
and the one-sided electrode 181 divided by the above @14:
Together with the above 111 molten solder layer 18), a molten solder layer (6) is formed over the entire area directly opposite the wafer (Figures V and 5 show the molten solder on the back side of the wafer) in a heated state. A method for forming a melting semi-free layer (6a) by directly supplying K [K] is shown below. This method involves heating a neutral Mg gas or a reducing gas such as hydrogen gas to a temperature above the melting point of the solder. Or, by virtue of the fact that the vacuum suction table m itself has a built-in heater, the wafer 111 is placed on the vacuum suction table iL, which is heated above the melting point of the solder, with xmis facing upward, and the vacuum suction table (9:) is rotated. At the same time as increasing the required rotational speed to the wafer ill, the ridged solder 90 is lowered from above the center position, and the wafer ill is rotated centrifugally.
The #melting solder layer (6a) of a predetermined thickness is formed by spreading the bath melting solder αα on the #l. Depending on the case, the wafer (1) may be immersed in a solder bath or may be formed by vacuum evaporation. The method for depositing a 1 m solder layer using vacuum evaporation is, for example, by holding a wafer parallel to plastic and netarium in a vacuum state of /f'' to /4 t, and depositing the desired solder ingot tp. /A method can be used to resistively heat a crucible made of stainless steel coil and cause evaporation bonding.Also, an electron gun evaporation bonding method is used in which a Vctar solder ingot is set in a water-cooled crucible and heated by concentrating electron beams. It may be by law.
また、仁の真空蒸着法忙よる場合ＧＣｔｆ被着半田の表
面状態を制御する為に蒸着チャンバーの中にアルゴン都
の不活性ガスを混入させることによって蒸着層の状態を
脆くするζｋが出来、債での半田の溶融分離性を向上さ
せた松、また浴−させなくても後工程の引伸し工程にて
容易に分皐出来る特徴もある。In addition, when the vacuum evaporation method is used, in order to control the surface condition of the GCTF deposited solder, an inert gas such as argon is mixed into the evaporation chamber to make the condition of the evaporated layer brittle. Pine has improved melting and separation properties of solder, and also has the feature that it can be easily separated in the subsequent drawing process without bathing.
以上の方法によって溶融半田層ｆ＠ｌ、ｒ６ａ）を形成
するが、４面電極１１１１ Ｋ接する溶融半田（ｌＩｌ
ｒ８ａ）Ｆｉ−れ性が非常に＆く、裏面電極（３）Ｋ強
固に密着する。一方格子状の溝＋４：ｒ４ｍ）に埋った
溶融半田（？） ｒ’Ｆａ）はウェーハ１１）のシリコ
ン面と接するため非常に濡れ性が騰（、従ってシリコン
面とは全く密着するこ七がないので、表面張力によって
裏面電極（３１に接する１１１−半田＋８１ （８ｍ）
に凝収する。そしてこの結果、格子状の溝１ｃｒ４亀）
が露出すると共に、も４図に示すように上記溝（４：に
よって区割された個々の裏面電極１８１上ｍａｌ固して
半田層（Ｉｌ’ｌを形成する。The molten solder layer f@l, r6a) is formed by the above method.
r8a) Fi has very low leakage and firmly adheres to the back electrode (3). On the other hand, the molten solder (?) r'Fa) buried in the lattice-shaped grooves +4:r4m) comes in contact with the silicon surface of the wafer 11), so its wettability is extremely high (therefore, the solder does not come into close contact with the silicon surface at all). Because there is no surface tension, the back electrode (111-solder in contact with 31 + 81 (8m)
to condense. And as a result, a grid-like groove 1 cr 4 turtles)
At the same time, as shown in FIG. 4, a solder layer (Il'l) is formed on the individual back electrodes 181 divided by the grooves (4).
尚、上述した半田ペーストを塗布する方法では、半田ペ
ースト塗布後、ウェーハ１１１′に加熱するため、工程
数が多く、時間もかが石が、溶融半田を直接供給する方
法では、単一工程であるため比較的短時間に行なわれる
。Note that the method of applying solder paste described above requires a large number of steps and is time-consuming because the wafer 111' is heated after applying the solder paste, whereas the method of directly supplying molten solder requires only a single step. Therefore, it is done in a relatively short period of time.
この後、必要に応じてウェーハ（１１を癩機ｖｃＳ）液
にて洗浄し、溶剤等を洗い蕩す・
そして後は露出した格子状の碑＋４： ｒ４１にθつて
９エーハ１１１をブレーキングしく折シ）＠２図に示す
単体の索子１１２１に分離する。After this, if necessary, wash the wafer (11 with leprosy machine vcS) liquid to remove the solvent, etc. Then, put the exposed grid-shaped monument +4: θ on r41 and brake 9 wafer 111. Folding) Separate into single cords 1121 shown in Figure 2.
以上説明した球にこの発明は、ウェーハの製面′１極側
より素子を区割する格子状の溝を鏝面電極より深く開設
してウェーハの材料面ｔ−嬉出させ、この格子状の溝に
対する溶融半田の濡れ性を急くしておき、ウェーハの裏
面の全域に鋳−半田層を供給した時、上記溶融半田をウ
ェーハの区割され良各１に面電憔上に轍路させると共に
、格子状の溝を旙出させ、この後この格子状の？ｌｔＫ
＆ってウェーハを切断して素子を分間するようｋした半
導体装置の製造方法に係シ、ウェーハの表面の全域に形
成した溶融半田層を各講子に対応した表面電極の半田層
に区割する工程と、溶融半田ノーより格子状害を露出σ
せる工程を同一に行なえ、この結果、裏面電極に半田Ｉ
ａｆ−形成した半導体装置を安価に提供すること
゛ができる。In the above-described sphere, the lattice-shaped grooves dividing the elements from the 1-pole side of the wafer are opened deeper than the trowel surface electrodes to make the wafer's material surface t-higher. The wettability of the molten solder to the grooves is made rapid, and when the cast solder layer is supplied to the entire back surface of the wafer, the molten solder is applied in a rut on each section of the wafer on the surface electrode. , let the lattice groove emerge, and then this lattice? ltK
In this method of manufacturing semiconductor devices, the wafer is cut into elements by cutting the wafer, and the molten solder layer formed over the entire surface of the wafer is divided into solder layers of surface electrodes corresponding to each section. The process of exposing the lattice damage from the molten solder
As a result, solder I is applied to the back electrode.
To provide af-formed semiconductor devices at low cost
゛ can be done.
更にウェーハの裏面に形成される半田層の厚務を均一に
することができる。Furthermore, the thickness of the solder layer formed on the back surface of the wafer can be made uniform.
襖／図乃至第２図はこの発明の半導体ａＪ飯の製造方法
ｔ−説明するための図を示し、第７図はウェーハの断面
図を示し、第２図はウェーハに格子状の信を開設した状
瞭をボす、第３図は半田ペーストを塗布して形成した溶
融半田層を示し、＠６図及び１ｇ２図は旙融した半田を
層状に供給して溶融半田層を形成する方法を示す。そし
て＠ダ図は上記夫々の溶融半田層を凝収させて形成した
一ｍｔ極上の半田層を示し、第５図は分−した単一の素
子を示す・
＋１１−１１＃−導体ウェーハ、！り・・索子、（３）
・・ｊＩ血電極、１４；ｒ４ａ）＊ ｅ格子状の溝、（
６１ｒ６ｍ）會ｅ溶融半田層、（ｔ）（）ａ）・・格子
状の４１ｃＪ１１りた浴−半田。
第１図Fusuma/Figures to Figure 2 are diagrams for explaining the method for manufacturing semiconductor aJ rice of this invention, Figure 7 is a cross-sectional view of a wafer, and Figure 2 is a wafer with grid-shaped wires. Fig. 3 shows a molten solder layer formed by applying solder paste, and Fig. 6 and 1g2 show a method of forming a molten solder layer by supplying melted solder in layers. show. ＠D diagram shows a solder layer of 1 mt maximum formed by condensing each of the above molten solder layers, and FIG. 5 shows a separated single element. Ri...Sakuko, (3)
... jI blood electrode, 14; r4a) * e grid-like groove, (
61r6m) Meeting e molten solder layer, (t) ()a)...grid-shaped 41cJ11 bath-solder. Figure 1
Claims (1)
＃ｋＵ電極匈に前記素子を区割する格子状の溝を１裏面
電極よシ深く開設して半導体ウエーノ）の材料面を露出
させ、次いでこの半導体ウエーノ１の裏面の全域に適意
・の半田な被着させ、この半導体ウェーハを加熱して浴
融半田層を形成し１或いは半導体ウェーへの＆面の全域
に溶融した半田を供給し、溶融半田が前記材料向に対し
て濡れ性が患い性′ｊ［を利用し、上記両溶融半田層の
凝固時、前記格子状のｌＺＫｍつた溶融半田を半導体ウ
ェーハの個々の表面電極上に凝収させると共に％該格子
状の溝を露出させ、この後格子状の溝に沿って半導体ク
エーノ・を切断して素子を分離するようＫしたことを特
徴とする半導体装置の製造方法・(1) jK of semiconductor wafer 1 with many elements formed
A lattice-shaped groove dividing the element into #kU electrodes is opened deeper than the back surface electrode 1 to expose the material surface of the semiconductor wafer 1, and then a suitable solder is applied to the entire back surface of the semiconductor wafer 1. The semiconductor wafer is heated to form a bath melted solder layer, and the molten solder is supplied to the entire surface of the semiconductor wafer, and the molten solder has a wettability to the material direction. When solidifying both of the molten solder layers, the lattice-shaped molten solder is condensed onto each surface electrode of the semiconductor wafer, and the lattice-shaped grooves are exposed. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is cut along lattice grooves to separate elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56115900A JPS5817636A (en) | 1981-07-23 | 1981-07-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56115900A JPS5817636A (en) | 1981-07-23 | 1981-07-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5817636A true JPS5817636A (en) | 1983-02-01 |
Family
ID=14673978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56115900A Pending JPS5817636A (en) | 1981-07-23 | 1981-07-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5817636A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0249442A (en) * | 1988-08-11 | 1990-02-19 | Toshiba Corp | Die bonding of optical semiconductor element |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4897484A (en) * | 1972-03-02 | 1973-12-12 | ||
| JPS5193867A (en) * | 1975-02-17 | 1976-08-17 | Handotaisochino seiho | |
| JPS5283070A (en) * | 1975-12-29 | 1977-07-11 | Seiko Instr & Electronics Ltd | Production of semiconductor device |
| JPS5513430A (en) * | 1978-07-11 | 1980-01-30 | Nec Corp | Test device for logic circuit |
| JPS5593293A (en) * | 1979-01-10 | 1980-07-15 | Hitachi Ltd | Method of soldering |
-
1981
- 1981-07-23 JP JP56115900A patent/JPS5817636A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4897484A (en) * | 1972-03-02 | 1973-12-12 | ||
| JPS5193867A (en) * | 1975-02-17 | 1976-08-17 | Handotaisochino seiho | |
| JPS5283070A (en) * | 1975-12-29 | 1977-07-11 | Seiko Instr & Electronics Ltd | Production of semiconductor device |
| JPS5513430A (en) * | 1978-07-11 | 1980-01-30 | Nec Corp | Test device for logic circuit |
| JPS5593293A (en) * | 1979-01-10 | 1980-07-15 | Hitachi Ltd | Method of soldering |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0249442A (en) * | 1988-08-11 | 1990-02-19 | Toshiba Corp | Die bonding of optical semiconductor element |
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