JPS60170933A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60170933A
JPS60170933A JP2780184A JP2780184A JPS60170933A JP S60170933 A JPS60170933 A JP S60170933A JP 2780184 A JP2780184 A JP 2780184A JP 2780184 A JP2780184 A JP 2780184A JP S60170933 A JPS60170933 A JP S60170933A
Authority
JP
Japan
Prior art keywords
electrode
substrate
semiconductor substrate
supporting member
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2780184A
Other languages
Japanese (ja)
Inventor
Katsuhiro Endo
遠藤 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP2780184A priority Critical patent/JPS60170933A/en
Publication of JPS60170933A publication Critical patent/JPS60170933A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To carry out photo etching without warpage and obtain highly accurate electrode pattern by previously executing selective processing for semiconductor substrate or electrode film provided at the surface by the photo etching, placing a brazing material between the substrate and supporting member and integrating them by dissolution and coagulation. CONSTITUTION:An electrode pattern is formed previously by the photo etching before coupling of the supporting member which has been carried out usually in the preceding stage in order to reinforce a semiconductor substrate. Thereby, a good pattern accuracy can be obtained. Namely, the substrate of gate turn-off thyristor is formed with 4-layer structure of P-N-P-N and a recessed surface 14 which enters the lower P type layer is formed to the upper most N type layer when the supporting member 4 is not yet bonded. Thereafter, an Al electrode film 7 is deposited on the entire part including such recessed surface, a cathode electrode 3 is formed at the upper most layer by the photo etching and a gate electrode is formed in separation to the next layer in the same way. Next, the supporting member 4 is fixed to the rear surface of substrate using an Al material 5.

Description

【発明の詳細な説明】 し発明の属する技術分野」 本発明は、例えはケートターンオフサイリスタ(以下O
TOナイリスタと記すうのように表面に複雑な形状の電
極を有する半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Technical field to which the invention pertains] The present invention relates to a turn-off thyristor (hereinafter referred to as O
The present invention relates to a method of manufacturing a semiconductor device having a complex-shaped electrode on its surface, such as a TO Nyristor.

し従来技術とその問題点〕 GTOザイリスタは電流の遮断を容易にするため、幅の
狭いカソード電極とゲート電極が互いに入シ組んだ形状
を肩する。第1図はGTO’−フイリスタの断面を示し
、pn pn 4層よシなるシリコン基板1のpベース
層11にはゲート電極2.nエミツタ層12にはカソー
ド電極3が設りられ、ゲート電極3はカソード電極4に
接触する図示しない電極板によって短絡されないように
nエミツタ層12に掘り込1れた凹面に形成される。一
方pエミッタ層13の側は、シリコンと熱膨張係数の近
似したモリブデンまたはタングステンからなる支持板4
に固定されるが、この固定は通常p形不純物となるアル
ミニウム′をろう材5とするろう付けによって行われる
Prior Art and Its Problems] In order to facilitate current interruption, the GTO Zyristor has a narrow cathode electrode and gate electrode that are intertwined with each other. FIG. 1 shows a cross section of a GTO'-filister, in which a p base layer 11 of a silicon substrate 1 consisting of four pn pn layers is provided with gate electrodes 2. A cathode electrode 3 is provided on the n-emitter layer 12, and the gate electrode 3 is formed on a concave surface dug into the n-emitter layer 12 so as not to be short-circuited by an unillustrated electrode plate that contacts the cathode electrode 4. On the other hand, on the side of the p emitter layer 13 is a support plate 4 made of molybdenum or tungsten, which has a thermal expansion coefficient similar to that of silicon.
This fixing is usually done by brazing using aluminum', which is a p-type impurity, as the brazing material 5.

第2図(a)〜(b)はこのようなGTOザイリスタの
従来の製造工程を示し、第1図と共通の部分には同一の
符号が付されている。まず図aに示すn形シリコン基板
1の両面からp形不純物を拡散させる1層11および1
3を形成しく図b)、さらに片面よりn形不純物を拡散
して4層構造とする(図C)。
FIGS. 2(a) and 2(b) show the conventional manufacturing process of such a GTO Zyristor, and parts common to those in FIG. 1 are given the same reference numerals. First, one layer 11 and one layer 1 in which p-type impurities are diffused from both sides of an n-type silicon substrate 1 shown in FIG.
3 (Figure b), and further diffuse n-type impurities from one side to form a four-layer structure (Figure C).

ついでゲート電極設置の凹面形成のため、光蝕刻技術を
用いて酸化膜6のパターンをつくシ(図dハエツチング
によυ凹面14を形成する(図e)。次に7リコン基板
1の補強の意味も兼ねて支持板4との間にアルミニウム
箔あるいはブルミニウム蒸着層からなるアルミニウム層
5をはさんでアルミニウムを融解させて合金化を行い、
基板1とモリブデンまたはタングステンからなる支持板
4と結合させる(図f)0次に表面全面をアルミニウム
の蒸着により電極膜7で被扱しく図g)、光蝕刻接触抵
抗を低下させるため強シンターを行う。しかしこのよう
な工程において、/リコンとモリブデンあるいはタング
ステンとの熱膨張係数が完全に一致し一〇いないため、
第2図tf)に示す合金化の際にバイメタル効果によシ
リコン基板1に曲りが生ずる。この曲シの度合はシリコ
ン基板工の口径が大きくなる程大きくなる。例えばシリ
コン基板1の厚さを0.91i1J4 、直径64韮、
モリブデン支持板4の厚さを3 Innとした場合、周
辺部のそりは中心部にくらべてo、 t amにも達す
る。
Next, in order to form a concave surface for installing a gate electrode, a pattern is made on the oxide film 6 using photoetching technology (Fig. d). A concave surface 14 is formed by etching (Fig. e). For this purpose, an aluminum layer 5 made of aluminum foil or a vapor-deposited aluminum layer is sandwiched between the support plate 4 and the aluminum is melted and alloyed.
The substrate 1 is bonded to a support plate 4 made of molybdenum or tungsten (Fig. f). Next, the entire surface is covered with an electrode film 7 by vapor deposition of aluminum (Fig. g), and strong sintering is applied to reduce the photoetching contact resistance. conduct. However, in such a process, the thermal expansion coefficients of silicon and molybdenum or tungsten do not completely match, so
During alloying as shown in FIG. 2 (tf), a bend occurs in the silicon substrate 1 due to the bimetallic effect. The degree of this bending increases as the diameter of the silicon substrate becomes larger. For example, the thickness of the silicon substrate 1 is 0.91i1J4, the diameter is 64mm,
When the thickness of the molybdenum support plate 4 is 3 Inn, the warpage at the peripheral portion reaches o, t am compared to the central portion.

このようなそシのある半導体基板1の表面の電極膜の光
蝕刻法によるパターン形成のために、第3図に示すよう
にアルミニウムA着膜7の上に感光材8を塗布した後マ
スク9を載せて光lOを当てて感光材8を選択的に感光
させる際マスク9と基板1の間に周辺部itど大きくな
るすき間11を生ずる。すき降の少ない中心部は感光パ
ターンの精度が良いが、すき間の大きい周辺部では光の
干渉が起こシ精度が低下する。従ってGTOザイリスタ
のように全面均一な分割電極を会費とする半導体装置で
は、大口径になる程電極形成が困難となる。
In order to form a pattern by photolithography on the electrode film on the surface of the semiconductor substrate 1 having such a groove, a photosensitive material 8 is coated on the aluminum A film 7 as shown in FIG. 3, and then a mask 9 is applied. When the photosensitive material 8 is selectively exposed by placing the mask 9 and exposing it to light 1O, a gap 11 is created between the mask 9 and the substrate 1, which becomes larger in the peripheral portion IT. The accuracy of the photosensitive pattern is good in the central area where there is little plowing, but in the peripheral area where there is a large gap, light interference occurs and the accuracy decreases. Therefore, in a semiconductor device such as a GTO Zyristor that requires divided electrodes that are uniform over the entire surface, the larger the diameter, the more difficult it becomes to form the electrodes.

〔発明の目的〕[Purpose of the invention]

本発明は、上述の欠点を除去して大口径の半導体基板の
表面に光蝕刻法によシ精度のよい電極バター7を形成す
ることができる半導体装置の製造方法を提供することを
目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-mentioned drawbacks and form an electrode butter 7 with high precision on the surface of a large-diameter semiconductor substrate by photolithography. .

〔発明の要点〕[Key points of the invention]

本発明は、半導体基板の一生表面側から光蝕刻法を用い
て半導体基板あるいは光面上の電極膜の選択的加工を行
う工程と、半導体基板と支持板との間にろう劇を挾み、
ろう材を融解、凝固させて半導体基板と支持体とを結合
する工程とを含む製造方法において、選択的加工工程を
行った後半導体基板と支持板との結合を行うことによっ
て上記の目的を達成する。
The present invention includes a step of selectively processing an electrode film on a semiconductor substrate or an optical surface using a photoetching method from the surface side of a semiconductor substrate, and interposing a wax film between a semiconductor substrate and a support plate.
In a manufacturing method that includes a step of melting and solidifying a brazing material to bond a semiconductor substrate and a support plate, the above objective is achieved by bonding the semiconductor substrate and the support plate after performing a selective processing step. do.

〔発明の実施例〕[Embodiments of the invention]

第4図tar〜(b)は本発明によるGTOサイリスタ
の製造工程を示し、第2図と共通の部分には同一の符号
が付されている。第4図ta+〜(C)においては第2
図(a)〜(c)と同様の工程でシリコン基板1に4層
構造を形成し、第4図(dl 、 (e)において第2
図(d)。
FIG. 4(b) shows the manufacturing process of a GTO thyristor according to the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In Fig. 4 ta+~(C), the second
A four-layer structure is formed on the silicon substrate 1 through the same steps as shown in FIGS.
Figure (d).

(e)と同様の工程で凹面14を形成する。このような
凹面14を有するシリコン基板lの上にアルミニウム電
極膜7を蒸着によシ被榎しく図f)、次いでリコ/基板
1とモリブデンまたはタングステンから成る支持板4と
をアルミニウム材5の合金化によシろう伺けする(図h
)。
A concave surface 14 is formed in the same process as in (e). An aluminum electrode film 7 is deposited on a silicon substrate 1 having such a concave surface 14 (as shown in FIG. I can ask you how to change it (Fig. h)
).

このような工程で製造を行うことによシ、光蝕刻法は平
面度のよい/リコン基板に対して実施されるため、元蝕
刻による電極パターン形成の精度を向上さぜることがで
きる。またシリコン基板1と支持板4とのろう付けの際
、アルミニウム電極7とpベース層12との接触抵抗の
低下も得られるので接触低下のための強7/ターは不要
になる。
By performing manufacturing using such a process, the photoetching method is performed on a silicon substrate with good flatness, so that the accuracy of electrode pattern formation by original etching can be improved. Further, when the silicon substrate 1 and the support plate 4 are brazed, the contact resistance between the aluminum electrode 7 and the p base layer 12 can be reduced, so that a strong 7/ter for reducing the contact is not necessary.

〔発明の効果J 本発明は、従来半導体基板の補強のため早い段階で行っ
ていた合金化による基板と支持板の結合工程を後に廻し
、光蝕刻法による加工工程を先に実施することにより、
そりのない状態での半導体基板に対し、光蝕刻法におけ
る露光を実施することができるため、中心部、同辺部共
同じ精度でパターン形成ができるため、特に複雑な電極
形状を有するGTOサイリスタなどの製造に極めて有効
に適用できる。また光蝕刻法でパターン形成された電極
のシンタ一工程が不要になるなど製造工程の合理化の面
でも有効であp、本発明によって得られる効果は極めて
大きい。
[Effect of the Invention J] The present invention postpones the process of bonding the substrate and support plate by alloying, which was conventionally performed at an early stage to strengthen the semiconductor substrate, to the later stage, and performs the processing process by photoetching first.
Since it is possible to perform exposure using the photoetching method on a semiconductor substrate without warping, it is possible to form a pattern with the same accuracy in the center and on the same side, so it can be used especially for GTO thyristors with complex electrode shapes, etc. It can be applied extremely effectively to the production of. It is also effective in streamlining the manufacturing process, such as eliminating the need for a step of sintering electrodes patterned by photoetching, and the effects obtained by the present invention are extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は(jToサイリスタの断面図、第2図は従来の
GTOサイリスタの製造工程を順次示す断面図、第3図
は従来の製造工程における光蝕刻法での露光の状態を示
す断面図、fs4図は本発明によるG’l’Oサイリス
タの製造工程の一実施例を順次示す断面図である。 l・・・シリコン基板、2・・ゲート電極、3・・カソ
ード電極、4・支持板、5・・・アルミニウム拐、7・
、・鉱極膜。 第1図 第2図
FIG. 1 is a cross-sectional view of the (jTo thyristor; FIG. 2 is a cross-sectional view sequentially showing the manufacturing process of a conventional GTO thyristor; FIG. 3 is a cross-sectional view showing the state of exposure by photolithography in the conventional manufacturing process; Fig. fs4 is a cross-sectional view sequentially showing an embodiment of the manufacturing process of the G'l'O thyristor according to the present invention. l...Silicon substrate, 2... Gate electrode, 3... Cathode electrode, 4... Support plate. , 5... Aluminum coating, 7.
,・Mineral electrode film. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] ■)半導体基板の一生表面側から光蝕刻法を用いて半導
体基板ゆるいは表面上の電極膜の選択的加工を行う工程
と、半導体基板と支持体との間にろう材を挾み、ろう材
を融解、凝固させて半導体基板と支持体とを結合する工
程とを含む製造方法において、前記選択的加工工程を行
った後半導体基板と支持板とのMiJ記結合工程を行う
ことを特徴とする半導体装置の製造方法。
■) A process of selectively processing the electrode film on the surface of the semiconductor substrate using photoetching from the surface side of the semiconductor substrate, and a process of sandwiching a brazing material between the semiconductor substrate and the support. A manufacturing method including a step of melting and solidifying the semiconductor substrate and the support plate to bond the semiconductor substrate and the support plate, characterized in that after performing the selective processing step, a MiJ bonding step of the semiconductor substrate and the support plate is performed. A method for manufacturing a semiconductor device.
JP2780184A 1984-02-16 1984-02-16 Manufacture of semiconductor device Pending JPS60170933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2780184A JPS60170933A (en) 1984-02-16 1984-02-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2780184A JPS60170933A (en) 1984-02-16 1984-02-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60170933A true JPS60170933A (en) 1985-09-04

Family

ID=12231076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2780184A Pending JPS60170933A (en) 1984-02-16 1984-02-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60170933A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0559625U (en) * 1992-11-30 1993-08-06 ティアック株式会社 Reel stand device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0559625U (en) * 1992-11-30 1993-08-06 ティアック株式会社 Reel stand device

Similar Documents

Publication Publication Date Title
JPS62160763A (en) Manufacture of semiconductor device in which metal film withthick contact electrode is provided on semiconductor
JPS60170933A (en) Manufacture of semiconductor device
US6387574B1 (en) Substrate for transfer mask and method for manufacturing transfer mask by use of substrate
JPS6222463B2 (en)
JPH10340852A (en) Substrate for transfer mask and manufacture of transfer mask using the substrate
JP3349001B2 (en) Metal film forming method
JPS6260234A (en) Manufacture of semiconductor diode element
JPS5816538A (en) Semiconductor device
JPH023918A (en) Manufacture of semiconductor device
JPH0231495B2 (en)
JPS58102564A (en) Manufacture of fet
JPS6159824A (en) Manufacture of semiconductor element
JPS581542B2 (en) Manufacturing method of semiconductor integrated circuit
JPH07273316A (en) Semiconductor device
JPS6226812A (en) Manufacture of semiconductor device
JPH06151884A (en) Semiconductor device and its manufacture
JPH01138762A (en) Formation of electrode
JPH05343580A (en) Lead frame
JPH0376235A (en) Semiconductor device
JPS5817636A (en) Manufacture of semiconductor device
JPS60157259A (en) Thin film transistor and manufacture thereof
JPH0497528A (en) Semiconductor device and manufacture thereof
JPS5854652A (en) Manufacture of semiconductor device
JPS5994851A (en) Manufacture of semiconductor integrated circuit
JPS62134922A (en) Manufacture of semiconductor device