JPS5994851A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the insulating performance of an oxide Si film preventing an electrode comprising multiple metallic layer from producing a defect such as discontinuity etc. by a method wherein a thermal oxide Si film is formed by means of selective etching the surface of an Si layer under a wiring pad and another oxide Si film is provided on the thermal oxide film. CONSTITUTION:An oxide Si film 18 is formed by means of forming a nitride Si film in a region of a wiring pad without performing the separating diffusion of an N type epitaxial Si layer 4 on a P type Si substrate 1. Any step difference of the surface of the synthetic oxide Si film 18 may be eliminated by means of providing a thermal oxide Si film 5 while the thick oxide Si film 18 may be provided under the wiring pad producing neither any pinholes nor a shortcircuit between a wiring and a transistor element at all. After providing a nitride Si film 12 coated by vapor growing process with an opening, a bump electrode comprising a Cr film 13, a Cu film 14, an Ni film 15 and an Sn-Pb solder alloy layer 16 may be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit including a bipolar element, and more particularly to an improvement in a method for forming an electrode made of two or more multiple metal layers in a wiring pad portion.

A manufacturing method commonly used in semiconductor integrated circuits including bipolar elements will be explained by illustrating the manufacturing steps in FIGS. 1a) to 1i).
A first Si oxide film 2 is formed by heat treatment in a high-temperature oxidizing atmosphere, and a window is opened by photoetching (FIG. 1a)). Next, a shallow n+ buried diffusion layer 3 is formed (first time). After once removing the Si oxide film 2, the Si substrate 1
0 surface by epitaxial growth method.
4 (Fig. 1c)). Second oxidized S1 film 5
By forming and photo-etching, a window is opened for p-type impurity diffusion to form mutually isolated n-shaded regions (
Figure 1 d)). The p-type isolation diffusion layer 6 is formed to be sufficiently deeper than the n-type epitaxial growth layer 4 (Fig. 1e).
). A window is formed in the Si oxide film 5 using the third photoetching step so that an npn transistor and a t transistor are formed in the isolation region having an n buried layer, and a base diffusion layer 7 is provided (the first Figure f)). Next, in the fourth photochip process, after opening a window in the Si oxide film 5, shallow n+ diffusion is performed to form npn) transistor emitter diffusion FVI.
8 and a collector diffusion layer 9 (FIG. 1g)).

In the fifth photo-etching process, terminal windows are opened to make ohmic contact for wiring in the n and p regions, and an A1 layer 10 is vacuum-deposited over the entire main surface of the St substrate 1 (
Figure 1h)). By the 6th photo etching process 9
The wiring of 11 layers 1o is completed, and the main part of the QF process is completed (Fig. 1i)).

FIG. 2 shows an example of the structure of the wiring pad portion and the bump electrode formed on the surface of the isolation region surrounded by the isolation diffusion layer 6 by the conventional manufacturing method as described above.

FIG. 2 shows a Cr film 13°Cu film film type 4 on the surface of which the Si nitride film 12 adhering to the aluminum wiring pad portion 11 has been selectively removed.
and Ni film 15f: deposited in this order, with the top layer being 5n-
It shows a structure in which bump electrodes are plated with Pb-based solder alloy. If a pinhole or the like exists in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, the current flowing into the semiconductor from the electrode will affect the operation of the transistor. This is provided to prevent this.

However, if there are pinholes or the like in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, not only will its insulation performance be impaired, but it will also be difficult to improve the degree of integration or chip □ Attempting to reduce the size also causes the following structural problems. That is, the third
The figure shows Cr film 13°Cu film film type 4Ni film 15 and 5n-
The wiring pad portion of the Pb-based solder alloy layer 16 equipped with bump electrodes made of multiple gold kite layers does not remain within the range of the isolation region surrounded by the isolation diffusion layer 6, but extends over the isolation diffusion layer 6. This is the case. A similar example of this is that the wiring pad part jumps over the isolation diffusion layer 6 and extends into the adjacent isolation region, or the wiring pad part jumps over the isolation diffusion layer 6 and extends to the adjacent isolation region, or the wiring pad part is placed on top of an impurity diffusion layer (not shown) used as a circuit resistance due to layout constraints such as wiring. There are some that reach out. In such a case, when providing the isolation diffusion layer 6 or an impurity diffusion layer (not shown), impurity diffusion is performed selectively, so that a step may not be formed in the Si oxide film 5 under the wiring hat portion. Inevitable. FIG. 4 shows a partial example of a defect in which when there is a step in the Si oxide film 5 and a bump electrode made of multiple metal layers is formed on the step, a defect occurs where the multiple metal layer becomes discontinuous at the step. This is an enlarged illustration. The possible cause of this defect is that the step difference that occurs in the Si oxide film 5 generally reaches 0.5 μm or more, whereas the electrodes made of multiple metal layers are designed to avoid cracks caused by thermal expansion. , its base metal Cr, C
Since the film thicknesses of u and Ni are often each 0.5 μm or less, if there is a dimensional difference of this degree, the base metal will not cover the stepped portions sufficiently. Fourth
The figure shows that the Cr film 13°Cu film type 4 coating is equivalent to being cut at the stepped portion. If this type of defect occurs, there is a drawback that the etching solution enters and corrodes during the electrode formation process, resulting in an open failure due to disconnection of the aluminum wiring. FIGS. 5 a) to 5 f) show the steps of manufacturing bump electrodes by repeating photo-etching steps, respectively. In step C), the Cr film 13. Four types of Cu film are deposited, and only Cu is selectively etched in step d), but if the above defects exist, the underlying CrM13t may also be eroded during etching. A similar situation may occur in the case of the nickel film 15 and the X7 bonding layer 16 performed in step e). Note that 17 represents photoresist)1.

If the base metal of the electrode is eroded in this way, a problem arises in that plating cannot be applied in the final electroplating process.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for forming an electrode that improves the insulation performance of a Si oxide film and does not cause defects such as discontinuous portions in an electrode made of multiple metal layers.

The present invention does not involve the formation of an isolation diffusion layer, which is generally used in the manufacturing method of semiconductor integrated circuits including bipolar elements.
The surface of the n-type epitaxial layer 5iffi under the wiring pad is selectively etched to form thermally oxidized StV, and furthermore, an oxidized Si film is provided on top of it to reinforce the insulating layer, and at the same time, this insulating layer is made to have no steps. This is achieved by

FIG. 6 shows an embodiment of the present invention, and is represented by the same reference numerals and names as in FIGS. 1 to 4.

According to the present invention, in FIG.
A Si nitride film (not shown) is selectively formed in the region of the wiring pad portion or a suitable wider region than the wiring pad portion without performing isolation and diffusion on the p-type St substrate 1 provided with the t-layer 4, and then etched. After etching to a depth of about 1 .mu.m, heat treatment is performed in a high temperature oxidizing atmosphere with the nitride S1 film (not shown) still attached to form an oxidized Si film 18 having the same thickness as the etching depth. Thereafter, the Si nitride film (not shown) is removed and a thermally oxidized Sl film 5 is again provided on the n-type epitaxial Si layer 4, thereby forming the synthesized S oxide.
The surface of the i-film has no steps, and a thick Si oxide film 18 can be provided under the wiring pad portion.

The reason for providing a thick oxide film under the wiring pad portion in this manner is to avoid the presence of pinholes in the Si oxide film and to prevent short circuits between the wiring portion and the transistor element. As shown in Fig. 7, it is clear from the plot representing the relationship between the St oxide film thickness and the pinhole density that the film thickness is 0.7.
This is because if the thickness is .mu.m or more, no pinholes will occur.

Thus, in the present invention, after opening the Si nitride film 12 deposited on the Si oxide film 5 by vapor phase growth, the Cr film 13.
Cu film 14. A bump electrode is formed of a Ni film 15 and 5n-Pbi alloy scraps 16. Also the 6th
As a modification of the figure, thermal oxidation s t is used instead of the Si oxide film 18.
It is also possible to use a combination of pl:γ and a film formed by vapor phase growth.

As explained above, according to the present invention, since no separation diffusion layer is provided under the wiring pad portion, a stepped Si film of Si oxide film that is generated due to the formation of the separation diffusion layer can be formed. As a result, a semiconductor integrated circuit with high insulation performance is produced without the occurrence of pinholes. This not only simplifies the manufacturing process of semiconductor integrated circuits including bipolar elements, but also greatly contributes to improving reliability.

In addition, the present invention is applicable not only to the formation of bump electrodes as described above, but also to the formation of wiring pads with electrodes made of multiple metal layers such as beam lead structures. It can also be applied to improving SIM. It can also be applied to the case where wiring pads are installed on other functional elements.

[Brief Description of the Drawings] Figures 1 a) to i) are process cross-sectional views showing a method of manufacturing a semiconductor integrated circuit, Figures 2 and 3 are cross-sectional views showing a conventional bump electrode structure, and Figure 4 is a cross-sectional view showing a conventional bump electrode structure. FIG. 5 a) to f) are enlarged cross-sectional views showing defects in the bump electrode; FIG. 6 is a cross-sectional view showing the bump electrode forming method according to the embodiment of the present invention; FIG. FIG. 3 is a diagram showing the relationship between the St oxide film and the pinhole density. 1 p-type St substrate, 2.5.18・Si oxide film, 4・
n-type epitaxial St scrap, 6 separation diffusion layer, single aluminum wiring pad, 12...Si nitride film, 13-Cr M
, 14-Cu film, 15-Ni film, 16-8 n-P
b is X7 alloy. -1-1 Kucho 2 Mouth Sai 30 -i4 Dayμ [Kukiku 2 /4 TS Figure 76 Figure T 7 Figure θ θ2 44 a Otsu 48 /
・θ9 appearance 4 Otsu silicon n odor, P spots

Claims (1)

[Claims] 1) - Forming a semiconductor layer of opposite conductivity type including a bipolar element on a conductivity type semiconductor substrate, and fixing an electrode made of multiple metal layers on the main surface of the semiconductor substrate having the semiconductor layer. In the method of manufacturing a semiconductor integrated circuit provided with a wiring pad, selectively etching a portion of the semiconductor layer to which the wiring pad is connected, and forming an oxide film at the etched portion;
A method of manufacturing a semiconductor integrated circuit, characterized in that the surfaces of the oxide film and the semiconductor layer are made to be flat, and the surfaces are further covered with a semiconductor oxide film. 2. A method for manufacturing a semiconductor integrated circuit, characterized in that the thickness of the oxide film laminated in the method according to claim 1 is 0.7 μm or more.