JPS5994851A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS5994851A JPS5994851A JP57205646A JP20564682A JPS5994851A JP S5994851 A JPS5994851 A JP S5994851A JP 57205646 A JP57205646 A JP 57205646A JP 20564682 A JP20564682 A JP 20564682A JP S5994851 A JPS5994851 A JP S5994851A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide
- layer
- oxide film
- wiring pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はバイポーラ素子を含む半導体集積回路の製造方
法、とくに配線パッド部に二層以上の多重金属層からな
る電極を形成する方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit including a bipolar element, and more particularly to an improvement in a method for forming an electrode made of two or more multiple metal layers in a wiring pad portion.
バイポーラ素子を含む半導体集積回路において通常行わ
れている製造方法を第1図a)〜i)に製造行程を例示
して説明するとp形St基板1の主表面上にSi基板1
を高温酸化性雰囲気で熱処理して第1回目の酸化Si膜
2の形成とフォトエツチングにより窓あけする(第1図
a))。次にn+埋込屓の浅い拡散層3を形成する(第
1回目))。酸化Si膜2を一旦除去した後Si基板1
0表面にエピタキシャル成長法によpn形S i m
4を形成する(第1図c))。第2回目の酸化S1膜5
の形成とフォトエツチングにより、互に分離されたn影
領域を形成するためのp形不純物拡散の窓あけをする(
第1図d))。p形分離拡散層6をn形エピタキシャル
成長層4より十分深くなるように形成する(第1図e)
)。n十埋込層を持つ分離領域にnpnト、tンジ
スタが形成されるように第3回目のフォトエツチング工
程を利用し酸化Si膜5に窓あけを行い、ベース拡散層
7を設ける(第1図f))。次に第4回目のフオトエツ
チップ工程で酸化Si膜5に窓あけした後、n+の浅イ
拡散を行いnpn )ランジスタのエミッタ拡散FVI
8とコレクタ拡散層9を設ける(第1図g))。A manufacturing method commonly used in semiconductor integrated circuits including bipolar elements will be explained by illustrating the manufacturing steps in FIGS. 1a) to 1i).
A first Si oxide film 2 is formed by heat treatment in a high-temperature oxidizing atmosphere, and a window is opened by photoetching (FIG. 1a)). Next, a shallow n+ buried diffusion layer 3 is formed (first time). After once removing the Si oxide film 2, the Si substrate 1
0 surface by epitaxial growth method.
4 (Fig. 1c)). Second oxidized S1 film 5
By forming and photo-etching, a window is opened for p-type impurity diffusion to form mutually isolated n-shaded regions (
Figure 1 d)). The p-type isolation diffusion layer 6 is formed to be sufficiently deeper than the n-type epitaxial growth layer 4 (Fig. 1e).
). A window is formed in the Si oxide film 5 using the third photoetching step so that an npn transistor and a t transistor are formed in the isolation region having an n buried layer, and a base diffusion layer 7 is provided (the first Figure f)). Next, in the fourth photochip process, after opening a window in the Si oxide film 5, shallow n+ diffusion is performed to form npn) transistor emitter diffusion FVI.
8 and a collector diffusion layer 9 (FIG. 1g)).
第5回目のフォトエツチング工程によりnおよびp領域
に配線用のオーム接触をするための端子用窓あけを行い
A1層10をSt基板1の主表面全面に真空蒸着する(
第1図h))。第6回目のフォトエツチング工程によ9
11層1oの配線が完成されクエハプロセスの主要な部
分は完了する(第1図i) )。In the fifth photo-etching process, terminal windows are opened to make ohmic contact for wiring in the n and p regions, and an A1 layer 10 is vacuum-deposited over the entire main surface of the St substrate 1 (
Figure 1h)). By the 6th photo etching process 9
The wiring of 11 layers 1o is completed, and the main part of the QF process is completed (Fig. 1i)).
以上のごとく通常の製造方法による分離拡散層6で囲ま
れた分離領域の表面上に形成される配線パッド部とバン
プ電極の構造を第2図に例示する。FIG. 2 shows an example of the structure of the wiring pad portion and the bump electrode formed on the surface of the isolation region surrounded by the isolation diffusion layer 6 by the conventional manufacturing method as described above.
第2図はアルミ配線パッド部11に被着した窒化Si膜
12を選択除去した表面上にCr膜13゜Cu膜膜種4
およびNi膜15f:この順に蒸着し、最上層は5n−
Pb系はんだ合金めっきをしてバンプ電極とした構造を
示している。このような分離領域は多重金属層からなる
電極と半導体表面との間に形成される酸化Si膜5にピ
ンホール等が存在する場合、電極から半導体内部に流入
する電流がトランジスタの動作に影響するのを阻止する
ために設けられるものである。FIG. 2 shows a Cr film 13°Cu film film type 4 on the surface of which the Si nitride film 12 adhering to the aluminum wiring pad portion 11 has been selectively removed.
and Ni film 15f: deposited in this order, with the top layer being 5n-
It shows a structure in which bump electrodes are plated with Pb-based solder alloy. If a pinhole or the like exists in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, the current flowing into the semiconductor from the electrode will affect the operation of the transistor. This is provided to prevent this.
しかしながら多重金属層からなる電極と半導体表面との
間に形成される酸化Si膜5にピンホール等が存在する
場合は、その絶縁性能が損われるのみならず、集積度を
向上させ、あるいはチップ □サイズを小さくしようと
すると次のような構造上の問題も生ずる。すなわち第3
図はCr膜13゜Cu膜膜種4Ni膜15および5n−
Pb系はんだ合金層16の多重金凧層からなるバンプ電
極を備えた配線パッド部が分離拡散層6で囲1れた分離
領域の範囲内にとどまらず、分離拡散層6の上にまで及
んでいる場合である。この類似例としては配線パッド部
が分離拡散層6を飛び超えて隣接する分離領域にまでか
かったり、あるいは配線などのレイアウトの制約から回
路抵抗として利用される図示してない不純物拡散層の上
に及んだりするものもある。このような場合分離拡散層
6や図示してない不純物拡散層を設ける際に、選択的に
不純物拡散を実施していることから、配線ハツト部の下
の酸化Si膜5に段差を生ずることが避けられない。第
4図は酸化Si膜5に段差がおる場合にその上に多重金
属層からなるバンプ電極を形成しようとするとき、段差
部において多重金属層が不連続になるという欠陥を生じ
る例を部分的に拡大して図示したものである。この欠陥
の原因として考えられることは酸化Si膜5に生ずる段
差が一般に0.5μm以上に達することが多いのに対し
、多重金属層からなる電極は、熱膨張によるクラックの
発生などを避けるために、その下地金属であるCr、C
uおよびNiの膜厚をそれぞれ0.5μm以下にするこ
とが多いので、この程度の寸法差があると段差部におけ
る下地金属の被覆が十分に行われないことにある。第4
図はCr膜13゜Cu膜膜種4被覆が段差部で切断され
た状態に等しいことを示している。この種欠陥が発生し
た場合、電極形成の工程でエツチング液が回り込んで浸
食しアルミ配線の断線によるオープン不良を生じたりす
る欠点を有する。第5図a)〜f)はフォトエツチング
工程を繰返し行うことにより、バンプ電極を製造する工
程をそれぞれ工程順に示したものであυ、工程C)では
Cr膜13.Cu膜膜種4蒸着し、工程d)でCuのみ
を選択的にエツチングすることになるが上記の欠陥が存
在すると、そのエツチングの際に下地のCrM13tで
も浸食してしまうことがある。同様のことは工程e)で
行うニッケル膜15およびはX7だめつき層16の場合
にも起こり得る。なお17はフオトレジス)1表わす。However, if there are pinholes or the like in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, not only will its insulation performance be impaired, but it will also be difficult to improve the degree of integration or chip □ Attempting to reduce the size also causes the following structural problems. That is, the third
The figure shows Cr film 13°Cu film film type 4Ni film 15 and 5n-
The wiring pad portion of the Pb-based solder alloy layer 16 equipped with bump electrodes made of multiple gold kite layers does not remain within the range of the isolation region surrounded by the isolation diffusion layer 6, but extends over the isolation diffusion layer 6. This is the case. A similar example of this is that the wiring pad part jumps over the isolation diffusion layer 6 and extends into the adjacent isolation region, or the wiring pad part jumps over the isolation diffusion layer 6 and extends to the adjacent isolation region, or the wiring pad part is placed on top of an impurity diffusion layer (not shown) used as a circuit resistance due to layout constraints such as wiring. There are some that reach out. In such a case, when providing the isolation diffusion layer 6 or an impurity diffusion layer (not shown), impurity diffusion is performed selectively, so that a step may not be formed in the Si oxide film 5 under the wiring hat portion. Inevitable. FIG. 4 shows a partial example of a defect in which when there is a step in the Si oxide film 5 and a bump electrode made of multiple metal layers is formed on the step, a defect occurs where the multiple metal layer becomes discontinuous at the step. This is an enlarged illustration. The possible cause of this defect is that the step difference that occurs in the Si oxide film 5 generally reaches 0.5 μm or more, whereas the electrodes made of multiple metal layers are designed to avoid cracks caused by thermal expansion. , its base metal Cr, C
Since the film thicknesses of u and Ni are often each 0.5 μm or less, if there is a dimensional difference of this degree, the base metal will not cover the stepped portions sufficiently. Fourth
The figure shows that the Cr film 13°Cu film type 4 coating is equivalent to being cut at the stepped portion. If this type of defect occurs, there is a drawback that the etching solution enters and corrodes during the electrode formation process, resulting in an open failure due to disconnection of the aluminum wiring. FIGS. 5 a) to 5 f) show the steps of manufacturing bump electrodes by repeating photo-etching steps, respectively. In step C), the Cr film 13. Four types of Cu film are deposited, and only Cu is selectively etched in step d), but if the above defects exist, the underlying CrM13t may also be eroded during etching. A similar situation may occur in the case of the nickel film 15 and the X7 bonding layer 16 performed in step e). Note that 17 represents photoresist)1.
このように電極の下地金属が浸食されてしまうと最終の
電気メツキ工程でメッキが施されなくなるという問題も
生じてくる。If the base metal of the electrode is eroded in this way, a problem arises in that plating cannot be applied in the final electroplating process.
本発明の目的は上述の欠点を除去して、酸化Si膜の絶
縁性能を高め多重金属層からなる電極に不連続部分など
の欠陥を生ずることのない電極形成方法を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for forming an electrode that improves the insulation performance of a Si oxide film and does not cause defects such as discontinuous portions in an electrode made of multiple metal layers.
本発明は一般にバイポーラ素子を含む半導体集積回路の
製造方法で用いられている分離拡散層の形成を伴わず、
配線パッド下のn形エピタキンヤル5iffiの表面を
選択エツチングして熱酸化StV、をつけ、さらにその
上に酸化Si膜を設けて絶縁層を補強し、同時にこの絶
縁層を段差のないものにすることにより達成される。The present invention does not involve the formation of an isolation diffusion layer, which is generally used in the manufacturing method of semiconductor integrated circuits including bipolar elements.
The surface of the n-type epitaxial layer 5iffi under the wiring pad is selectively etched to form thermally oxidized StV, and furthermore, an oxidized Si film is provided on top of it to reinforce the insulating layer, and at the same time, this insulating layer is made to have no steps. This is achieved by
第6図は本発明の実施例を示すもので第1図〜第4図ま
での同一符号と同一名称で表わしている。FIG. 6 shows an embodiment of the present invention, and is represented by the same reference numerals and names as in FIGS. 1 to 4.
本発明によれば第6図において、n形エピタキシャルS
t層4を備えたp形St基板1に分離拡散を施すことな
く、配線パッド部の領域またはそれ以上の適当な広い領
域に選択的に図示してない窒化Si膜を形成してエツチ
ングする。約1μm程度の深さにエツチングした後、図
示してない窒化S1膜をつけたまま、高温酸化性雰囲気
の下で熱処理して、エツチング深さと同じ膜厚を有する
酸化Si膜18を生成させる。然る後図示してない窒化
Si膜を除去し再びn形エピタキシャルSi層4の上に
熱酸化Sl膜5を設けることにより、合成された酸化S
i膜の表面は段差を有することなく、しかも配線パッド
部の下には厚い酸化Si膜18を備えることができる。According to the present invention, in FIG.
A Si nitride film (not shown) is selectively formed in the region of the wiring pad portion or a suitable wider region than the wiring pad portion without performing isolation and diffusion on the p-type St substrate 1 provided with the t-layer 4, and then etched. After etching to a depth of about 1 .mu.m, heat treatment is performed in a high temperature oxidizing atmosphere with the nitride S1 film (not shown) still attached to form an oxidized Si film 18 having the same thickness as the etching depth. Thereafter, the Si nitride film (not shown) is removed and a thermally oxidized Sl film 5 is again provided on the n-type epitaxial Si layer 4, thereby forming the synthesized S oxide.
The surface of the i-film has no steps, and a thick Si oxide film 18 can be provided under the wiring pad portion.
このように配線パッド部の下に厚い酸化膜を設けるのは
酸化Si膜にピンホールの存在金避け、配線部とトラン
ジスタ素子とのショートが生じないようにするためであ
る。第7図に示すように酸化St膜厚とピンホール密度
との関係を表わす曲想から明らかなように膜厚を0.7
μm以上とすればピンホールは発生しないからである。The reason for providing a thick oxide film under the wiring pad portion in this manner is to avoid the presence of pinholes in the Si oxide film and to prevent short circuits between the wiring portion and the transistor element. As shown in Fig. 7, it is clear from the plot representing the relationship between the St oxide film thickness and the pinhole density that the film thickness is 0.7.
This is because if the thickness is .mu.m or more, no pinholes will occur.
かくして本発明では、酸化Si膜5の上に気相成長法で
被着した窒化Si膜12を窓あけした後、Cr膜13.
Cu膜14.Ni膜15および5n−Pbi伏A7だ合
金屑16からなるバンプ電極を形成している。また第6
図の変形例として酸化Si膜18の代りに熱酸化s t
pl:γと気相成長法による被膜とを組合わせて用い
ることもできる。Thus, in the present invention, after opening the Si nitride film 12 deposited on the Si oxide film 5 by vapor phase growth, the Cr film 13.
Cu film 14. A bump electrode is formed of a Ni film 15 and 5n-Pbi alloy scraps 16. Also the 6th
As a modification of the figure, thermal oxidation s t is used instead of the Si oxide film 18.
It is also possible to use a combination of pl:γ and a film formed by vapor phase growth.
以上説明したごとく、本発明によれば配線パッド部の下
に分合[を拡散層を設けていないから、分離拡散層の形
成に起因して生ずる酸化Si膜の段差化Si膜を形成し
であるので、ピンホールの発生もなく、絶縁性能の高い
半導体集積回路がイSられる。このことはバイポーラ素
子を含む半導体集積回路の製造工程を簡素化するのみな
らず信頼性の向上に大きく寄与するものである。As explained above, according to the present invention, since no separation diffusion layer is provided under the wiring pad portion, a stepped Si film of Si oxide film that is generated due to the formation of the separation diffusion layer can be formed. As a result, a semiconductor integrated circuit with high insulation performance is produced without the occurrence of pinholes. This not only simplifies the manufacturing process of semiconductor integrated circuits including bipolar elements, but also greatly contributes to improving reliability.
また本発明はいままで説明したバンプ電極形成の場合は
もちろん、ビームリード構造のような多重金属層からな
る電極を備えた配線パッドの形成のほかに、ピンホール
が懸念される配線金属下の酸化SIMの改良にも応用で
きる。その他機能素子上に配線パッドを設置する場合に
も応用が可能となる。In addition, the present invention is applicable not only to the formation of bump electrodes as described above, but also to the formation of wiring pads with electrodes made of multiple metal layers such as beam lead structures. It can also be applied to improving SIM. It can also be applied to the case where wiring pads are installed on other functional elements.
【図面の簡単な説明】
第1図a)〜i)は半導体集積回路の製造方法を示す工
程断面図、第2図、第3図は従来のバンプ電極構造を示
す断面図、第4図はバンプ電極の欠陥を示す拡大断面図
、第5図a)〜f)はバンプ電極の製造工程を示す断面
図、第6図は本発明の実施例によるバンプ電極形成方法
を示す断面図、第7Fit酸化St膜とピンホール密度
の関係を表わす線図である。
1 p形St基板、2.5.18・酸化Si膜、4 ・
n形エピタキシャルSt屑、6 分離拡散層、1ドアル
ミ配線パッド、12・・・窒化Si膜、13−Cr M
、 14−Cu膜、15−Ni膜、16−8 n−P
bはX7だ合金。
−1−1口
丁 2 口
才30
−i4 日
μ[葺く2
/4
TS 図
76 図
T 7 図
θ θ2 44 a乙 48 /
・θ9貌4乙シリコンn臭に、P斑[Brief Description of the Drawings] Figures 1 a) to i) are process cross-sectional views showing a method of manufacturing a semiconductor integrated circuit, Figures 2 and 3 are cross-sectional views showing a conventional bump electrode structure, and Figure 4 is a cross-sectional view showing a conventional bump electrode structure. FIG. 5 a) to f) are enlarged cross-sectional views showing defects in the bump electrode; FIG. 6 is a cross-sectional view showing the bump electrode forming method according to the embodiment of the present invention; FIG. FIG. 3 is a diagram showing the relationship between the St oxide film and the pinhole density. 1 p-type St substrate, 2.5.18・Si oxide film, 4・
n-type epitaxial St scrap, 6 separation diffusion layer, single aluminum wiring pad, 12...Si nitride film, 13-Cr M
, 14-Cu film, 15-Ni film, 16-8 n-P
b is X7 alloy. -1-1 Kucho 2 Mouth Sai 30 -i4 Dayμ [Kukiku 2 /4 TS Figure 76 Figure T 7 Figure θ θ2 44 a Otsu 48 /
・θ9 appearance 4 Otsu silicon n odor, P spots
Claims (1)
電形の半導体層を形成し、該半導体層を有する前記半導
体基板の主表面上に多重金属層からなる電極を固着する
配線パッドを設けた半導体集積回路の製造方法において
、前記配線パッドが接続される部分の前記半導体層を選
択エツチングし、該エツチング個所に酸化膜を形成し、
該酸化膜と前記半導体層の表面が=平面をなすようにし
、さらに、それらの表面を半導体の酸化膜により覆うこ
とを特徴とする半導体集積回路の製造方法。 2、特許請求の範囲第1項記載の方法において積層され
た酸化膜の厚さが0.7μm以上であることを特徴とす
る半導体集積回路の製造方法。[Claims] 1) - Forming a semiconductor layer of opposite conductivity type including a bipolar element on a conductivity type semiconductor substrate, and fixing an electrode made of multiple metal layers on the main surface of the semiconductor substrate having the semiconductor layer. In the method of manufacturing a semiconductor integrated circuit provided with a wiring pad, selectively etching a portion of the semiconductor layer to which the wiring pad is connected, and forming an oxide film at the etched portion;
A method of manufacturing a semiconductor integrated circuit, characterized in that the surfaces of the oxide film and the semiconductor layer are made to be flat, and the surfaces are further covered with a semiconductor oxide film. 2. A method for manufacturing a semiconductor integrated circuit, characterized in that the thickness of the oxide film laminated in the method according to claim 1 is 0.7 μm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57205646A JPS5994851A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57205646A JPS5994851A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5994851A true JPS5994851A (en) | 1984-05-31 |
Family
ID=16510334
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57205646A Pending JPS5994851A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5994851A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01123440A (en) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | Semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631893A (en) * | 1979-08-23 | 1981-03-31 | Mitsubishi Heavy Ind Ltd | Device to reduce rolling in ship |
JPS5733704A (en) * | 1980-08-06 | 1982-02-23 | Niihama Ponpu Seisakusho Kk | High temperature drain recovery apparatus |
-
1982
- 1982-11-24 JP JP57205646A patent/JPS5994851A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5631893A (en) * | 1979-08-23 | 1981-03-31 | Mitsubishi Heavy Ind Ltd | Device to reduce rolling in ship |
JPS5733704A (en) * | 1980-08-06 | 1982-02-23 | Niihama Ponpu Seisakusho Kk | High temperature drain recovery apparatus |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01123440A (en) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | Semiconductor device |
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