JPS5994850A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5994850A
JPS5994850A JP57205645A JP20564582A JPS5994850A JP S5994850 A JPS5994850 A JP S5994850A JP 57205645 A JP57205645 A JP 57205645A JP 20564582 A JP20564582 A JP 20564582A JP S5994850 A JPS5994850 A JP S5994850A
Authority
JP
Japan
Prior art keywords
film
oxide
layer
oxide film
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57205645A
Other languages
Japanese (ja)
Inventor
Misao Saga
佐賀 操
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP57205645A priority Critical patent/JPS5994850A/en
Publication of JPS5994850A publication Critical patent/JPS5994850A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the insulating performance of an oxide Si film preventing an electrode comprising multiple metallic layer from producing a defect such as discontinuity etc. by a method wherein, in a semiconductor integrated circuit containing bipolar elements, a vapor grown oxide Si film is deposited on a thermal oxide film on the surface of an Si layer. CONSTITUTION:An aluminum wiring 11 is provided on a P type Si substrate 1 with an N type epitaxial Si layer 4 without performing separated diffusion through the intermediary of an oxide Si film 5 produced by heat-treatment under high temperature oxidative atmosphere and another oxide Si film 18 deposited by chemical vapor growing process and after providing a nitride Si film 12 coated by vapor growing process with an opening, a bump electrode comprising an Cr film 13, a Cu film 14, an Ni film 15 and an Sn-Pb solder alloy layer 16 is formed. Through these procedures, any step difference due to formation of the separated diffusion layer may be eliminated because any separated diffusion layer need not be formed at all since the shortcircuit between a wiring and transistor elements due to pinholes in the oxide Si film 5 is restrained by means of depositing the vapor grown oxide Si film 18 to improve the insulating performance.

Description

【発明の詳細な説明】 本発明はバイポーラ素子を含む半導体集積回路、とくに
配線パッド部(こ二層以上の多産金属層からなる電極を
形成した半導体集積回路の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor integrated circuit including a bipolar element, and particularly in a semiconductor integrated circuit in which a wiring pad portion (an electrode made of two or more metal layers) is formed.

バイポーラ素子を含む半導体集積回路においで通常行わ
れでいる製造方法を+第1回目)〜A)+に製造工程を
例示して説明するとp形Si基板1を高温酸化性雰囲気
で熱処理して第1回目の酸化Si膜2の形成とフォトエ
ツチングにより窓あけする(第1回目))。次にn+埋
込層の浅い拡散J曽3を形成する(第1図b))。酸化
Sii 2を一旦除去した後Si基板1の表面にエピタ
キシャル成長法によりn形Si層4を形成する(第1回
目))。第2回目の酸化S1膜5の形成とフォトエツチ
ングにより、互に分離されたn形憤域を形成するための
p形不純物拡散の窓あけをする(第1回目))。p形分
離拡散層6をn形エピタキシャル成長層4より十分深く
なるように形成する(第1回目) )。nM込層を持つ
分離領域にnpn トランジスタが形成されるように第
3回目のフォトエツチング工程を利用し酸化S1膜5に
窓あけを行い、ペース拡赦層7を設ける(第1図f))
。次に第4回目のフォトエツチング工程で酸化Si膜5
に窓あけした後、nの浅い拡散を行いnpn’)ランジ
スタ拡散層8とコレクタ拡散層9を設ける(第1図g)
)。第5回目のフォトエツチング工程によりnおよびp
領域に配線用のオーム接触をするための端子用窓あけを
行いAI層lO昔をSi基板lの主表面全面に真窒蒸着
する(第1図h))。第6回目のフォトエツチング工程
によりAI層10の配線が完成されウエノ・プロセスの
主要な部分は完了する(ii41図i))。
The manufacturing method normally carried out in semiconductor integrated circuits including bipolar elements will be explained by illustrating the manufacturing steps in Part 1) to A). A window is opened by forming the Si oxide film 2 for the first time and photo etching (first time). Next, a shallow diffusion Jso 3 of the n+ buried layer is formed (FIG. 1b)). After the oxidized Sii 2 is once removed, an n-type Si layer 4 is formed on the surface of the Si substrate 1 by epitaxial growth (first time). By the second formation of the oxidized S1 film 5 and photoetching, a window is opened for p-type impurity diffusion to form mutually separated n-type regions (first time). The p-type isolation diffusion layer 6 is formed to be sufficiently deeper than the n-type epitaxial growth layer 4 (first time). A third photo-etching process is used to open a window in the oxide S1 film 5 so that an npn transistor is formed in the isolation region having the nM-containing layer, and a pace expansion layer 7 is provided (FIG. 1f))
. Next, in the fourth photoetching step, the Si oxide film 5
After opening a window, shallow diffusion of n is performed to form a transistor diffusion layer 8 and a collector diffusion layer 9 (npn') (Fig. 1g).
). The fifth photoetching process removes n and p.
A window for a terminal is made in the area for making an ohmic contact for wiring, and an AI layer 10 is deposited with pure nitrogen over the entire main surface of the Si substrate 1 (FIG. 1h)). By the sixth photo-etching step, the wiring of the AI layer 10 is completed, and the main part of the Ueno process is completed (Fig. ii 41 i)).

以上のごとく通常の製造方法による分離拡散層6で囲す
れた分離領域の表面上に形成される配線パッド部とバン
プ電極の構造を第2図に例示する。
FIG. 2 shows an example of the structure of the wiring pad portion and the bump electrode formed on the surface of the isolation region surrounded by the isolation diffusion layer 6 by the conventional manufacturing method as described above.

82図はアルミ配線パッド部11に破着した菫化8i膜
12を選択除去した表面上にOr膜13 、 Ou膜1
4.およびINi膜15をこの順に蒸着し、最上層は5
n−Pb系はんだ合金めっきをしてバング電極とした構
造を示している。このような分離領域は多重金属層から
なる′α極と半導体表面との間に形成される酸化Si族
5にピンホール等が存在する場合、電極から半導体内部
に流入する電流がトランジスタの動作に影響するのを阻
止するために設けられるものである。
In Figure 82, an Or film 13 and an Ou film 1 are formed on the surface after selectively removing the phosphorized 8i film 12 that has adhered to the aluminum wiring pad portion 11.
4. and INi film 15 are deposited in this order, with the top layer being 5
It shows a structure in which a bang electrode is plated with n-Pb solder alloy. If a pinhole or the like exists in the Si oxide group 5 formed between the 'α pole made of multiple metal layers and the semiconductor surface, the current flowing into the semiconductor from the electrode may affect the operation of the transistor. This is provided to prevent any influence from occurring.

しかしながら多重金属層からなる電極と半導体表面との
間に形成される酸化Si膜5にピンホール等が存在する
場合は、その絶縁性能が損われるのみならず、集績就を
向上させ、あるいはチップサイズを小さくしようとする
と次のような構造上の問題も生ずる。すなわち第3図は
OrN 13 、 Ou膜14、Ni膜15および5n
−Pbiはんだ合金層16の多重金属層からなるバング
電極を備えた配線パッド部が分離拡散層6で囲まれた分
離領域のれ曲内(ことどまらす、分配拡散層6の上に韮
で及んでいる場合てめる。この類似例としては配線パッ
ド部が分離拡散層6を飛び超えて、瞬接する分離領域に
までかかったり、あるいは配線などのレイアウトの制約
から回路抵抗として利用される図示しでない不純物拡散
層の上に及んだりするものもある。このような場合分離
拡散層6や図示してない不純物拡散層を設ける際に、選
択的に不純物拡散を実施していること71)ら、配線バ
ンド部の下の酸化Si膜5に段差を生ずることが避けら
れない。第4図はば化Si膜5に段差がある場合にその
上に多重金属層からなるバンプ電極を形成しようとする
とき、段差部において多重金属層が不連続になるという
欠陥を生じる例を部分的に拡大して図示したものである
。この欠陥の原因として考えられることは酸化Si膜5
に生ずる段差が一般に0.5μm以上に達することが多
いのに対し、多重金属層からなる電極は、熱膨張による
クシツクの発生などを避けるために、その下地金属であ
るOr 、 OuおよびNiの膜厚をそれぞれ0.5μ
m以下にすることが多いので、この程度の寸法差がある
と段差部における下地金属の被覆が十分に行われないこ
とにある。
However, if pinholes or the like exist in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, not only will the insulation performance be impaired, but the performance of the chip Attempting to reduce the size also causes the following structural problems. That is, FIG. 3 shows OrN 13 , Ou film 14 , Ni film 15 and 5n
- The wiring pad portion with the bang electrode made of multiple metal layers of the Pbi solder alloy layer 16 extends within the curve of the isolation region surrounded by the isolation diffusion layer 6 (limited to above the distribution diffusion layer 6). Similar examples include cases where the wiring pad part jumps over the isolation diffusion layer 6 and extends into the isolation region that is in momentary contact, or where the wiring pad part is used as a circuit resistor due to layout constraints such as wiring. In some cases, the impurity diffusion layer 6 or the impurity diffusion layer (not shown) is selectively diffused when providing the separation diffusion layer 6 or an impurity diffusion layer (not shown). , it is inevitable that a step will be formed in the Si oxide film 5 under the wiring band portion. FIG. 4 shows a partial example of a defect in which the multi-metal layers become discontinuous at the step portion when a bump electrode made of multiple metal layers is formed on the Si substrate 5 with a step difference. This is an enlarged illustration. The possible cause of this defect is the Si oxide film 5.
In contrast, electrodes made of multiple metal layers generally require a layer of Or, Ou, and Ni, which is the base metal, to avoid wrinkles caused by thermal expansion. Thickness 0.5μ each
Since the thickness is often less than m, if there is a dimensional difference of this degree, the underlying metal will not be sufficiently coated at the stepped portion.

第4図はOr膜13.Ou膜14の被覆が段差部で切断
された状態に寺しいことを示しでいる。この棟欠陥が発
生した場合、電極形成の工程でエツチング液が回り込ん
で浸食しアルミ配線の断勝によるオープン不良を生じた
りする欠点を有する。第5回目)〜f)はフォトエツチ
ング工程を繰返し行うことにより、バンプ電極を製造す
る工程をそれぞれ工程順に示したものであり、工程C)
ではOr膜13゜Ou膜14を蒸着し、工程d)でOu
のみを選択的にエツチングすることになるが上記の欠陥
が存在すると、そのエツチングの際に下地のOr膜13
までも浸食してしまうことがある。同様のことは工程e
)で行うニッケル膜15およびはんだめっき層16の場
合にも起こり得る。なお17はフォトレジストを表わす
。このように電極の下地金属が浸食されでしまうと最終
の電気メツキ工程でメッキが施されなくなるという問題
も生じでくる。
FIG. 4 shows the Or film 13. This clearly shows that the coating of the Ou film 14 is cut off at the step portion. If this ridge defect occurs, the etching solution may enter and erode the electrode during the electrode formation process, resulting in an open defect due to breakage of the aluminum wiring. Part 5) to f) show the steps of manufacturing bump electrodes by repeating the photo-etching process in the order of steps, and step C)
Then, the Or film 13° and the Ou film 14 are deposited, and in step d) the Ou film 14 is deposited.
However, if the above defects exist, the underlying Or film 13 will be etched during etching.
It may even erode. The same thing is in step e.
) can also occur in the case of the nickel film 15 and solder plating layer 16. Note that 17 represents a photoresist. If the underlying metal of the electrode is eroded in this way, a problem arises in that plating cannot be applied in the final electroplating process.

連続部分などの欠陥を生ずることのない電極を形成した
半導体集積回路を提供することにある。
It is an object of the present invention to provide a semiconductor integrated circuit in which electrodes are formed without causing defects such as continuous parts.

本発明は一般にバイポーラ素子を含む半導体集積回路で
用いられている分離拡散を’、f < L、”形エピタ
キシャルSi層表面の熱酸化膜をさらに気相される。
In the present invention, a thermal oxide film on the surface of an epitaxial Si layer is further vapor-phased by separating diffusion generally used in semiconductor integrated circuits including bipolar elements.

第6図は本発明の実施例を示すbので第1図〜第4図ま
での同一符号と同一名称て表わしでいる。
Since FIG. 6 shows an embodiment of the present invention, the same reference numerals and names as in FIGS. 1 to 4 are used.

本発明によれば第6図において、n形エピタキシた ギルSi層45:備え物p形Si基板1に分離拡散を轡
積させた0、2μm8度の酸化Si膜18を介しで、ア
ルミ配線11を設け、その上に気相成長法で被着した窒
化Si膜125−窓あけした後、Or、[13、0ui
1114.Ni膜15,5n−Pbはんだ合金層16か
らなるバンプ電極を形成したものである。
According to the present invention, in FIG. 6, an n-type epitaxial gill Si layer 45: an aluminum wiring 11 is formed through a 0.2 μm 8 degree Si oxide film 18 on which isolation diffusion is accumulated on the p-type Si substrate 1. After opening the Si nitride film 125 deposited on it by vapor phase epitaxy, Or, [13,0ui
1114. A bump electrode is formed of a Ni film 15 and a 5n-Pb solder alloy layer 16.

この構成において酸化S1膜5の上に気相成長酸化st
膜isを積層しているのは、酸化Si膜にピンホールが
存在している場合に酸化8i膜を補強し電極とトランジ
スタ等機能素子とのショートが生じないようにしたため
である。は化Si膜5だけでは第7図の酸化S1膜厚と
ピンホール密度との関係を表わす白側が示すように、膜
厚が0.7μm以下のときはピンホールが皆無にならす
しかも不純物拡散などの工程をさらに棟返し行うことに
より膜厚が1μm以上となってもピンホールが新たに発
生する可能性もあるので、この酸化Si膜5の上に02
μm以上の気相成長酸化Si膜18を被着してピンホー
ルの問題を解決しでいる。また第6図の変形例とらの被
膜を組合わせて用いることもできる。
In this configuration, vapor phase growth oxide st is formed on the oxide S1 film 5.
The reason why the film IS is laminated is to reinforce the 8i oxide film and prevent a short circuit between the electrode and a functional element such as a transistor when a pinhole exists in the Si oxide film. As shown by the white side of the relationship between the S1 oxide film thickness and the pinhole density in Figure 7, if the Si oxide film 5 is used alone, there will be no pinholes when the film thickness is 0.7 μm or less, and impurity diffusion will occur. Even if the film thickness becomes 1 μm or more by repeating the process again, new pinholes may occur, so 02
The problem of pinholes has been solved by depositing a vapor phase grown Si oxide film 18 with a thickness of .mu.m or more. Further, the coatings of the modified example shown in FIG. 6 can also be used in combination.

以上説明したごとく本発明によれば、酸化Si膜に気相
成長8i薄膜を被着して、ピンホールによる配線部とト
ランジスタ素子とのショートを抑制し、絶縁性能を高め
であるので分離拡散層を形成する必要がなく、シたがっ
て分離拡散層の形成に起因して生ずる酸化膜の段差のた
めに、配線パッド部における磁極下地金属に欠陥が生ず
るという心配もない。また浅い拡散の拡散抵抗上に配線
パッド部を設けることも可能に1よる。このように本発
明はバイポーラ素子を含む半導体集積回路の製造工程を
簡素化するのみならず、信頼性の向上に大きく寄与する
ものである。
As explained above, according to the present invention, a vapor-grown 8i thin film is deposited on a Si oxide film to suppress short-circuits between wiring parts and transistor elements due to pinholes, and to improve insulation performance. Therefore, there is no fear that defects will occur in the magnetic pole base metal in the wiring pad portion due to the step difference in the oxide film caused by the formation of the isolation diffusion layer. Further, according to 1, it is also possible to provide a wiring pad portion on a shallowly diffused diffusion resistor. As described above, the present invention not only simplifies the manufacturing process of semiconductor integrated circuits including bipolar elements, but also greatly contributes to improving reliability.

また本発明はいままで説明したバンプ電極形成の場合は
もちろん、ビームリード構造のような多重金属層からな
る電極を備えた配線パッドの形成のほかに、ピンポール
が懸念される配線全域下の酸化Si膜の改良にも応用で
きる。その他、機能素子上に配線パッドを設置する場合
にも応用か可能となる。
In addition, the present invention is applicable not only to the formation of bump electrodes as described above, but also to the formation of wiring pads with electrodes made of multiple metal layers such as beam lead structures. It can also be applied to improving membranes. In addition, it can also be applied to the case where wiring pads are installed on functional elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a)〜i)は半導体集積回路の製造方法を示す工
程断面図、第2図、第3図は従来のバンプ′電極構造を
示す断面図、第4図はパンダ電極の欠陥を示す拡大断面
図、第5図a)〜Dはバンプ′電極の製造工8を示す断
面図、第6図は本発明の実施例によるバンプ電極を示す
断面図、第7図は酸化Si膜とピンホール密度の関係を
表イつす線図である。 にP形Si基板、2.5:m化Sr膜、4:n形エビタ
キ7ヤルSi層、6:分離拡散層、11:AI配線パッ
ド、12:窒化Si膜、13:Or膜、14:Cu膜、
15m+’lt膜、15:5n−Pbはんだ合金層、1
8:気相成長酸化Si膜。 lf′l   口 T 2 口 T3 口 才 4 口 /4 才!50 T 6 図
Figures 1 a) to i) are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit, Figures 2 and 3 are cross-sectional views showing a conventional bump' electrode structure, and Figure 4 shows defects in the panda electrode. Expanded cross-sectional views, FIGS. 5a) to 5D are cross-sectional views showing the manufacturing process 8 of the bump' electrode, FIG. 6 is a cross-sectional view showing the bump electrode according to the embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the silicon oxide film and the pin. FIG. 3 is a diagram showing the relationship between hole densities. P-type Si substrate, 2.5: mSr film, 4: n-type nitride seven-layer Si layer, 6: isolation diffusion layer, 11: AI wiring pad, 12: Si nitride film, 13: Or film, 14: Cu film,
15m+'lt film, 15:5n-Pb solder alloy layer, 1
8: Vapor-phase grown Si oxide film. lf'l Mouth T 2 Mouth T3 Mouth Sai 4 Mouth/4 years old! 50 T 6 figure

Claims (1)

【特許請求の範囲】 1)−導電形の半導体基板にバイボー2素子を含む逆導
電形の半導体層を形成し、該半導体層を有する前記半導
体基板の主表面上に多重金属からなる電極を固着する配
線パッドを設けた半導体集積回路において、前記逆導電
形半導体層表面に形成された熱酸化膜と該熱酸化膜上に
暴績させた気相成長半導体酸化膜により、前記配線パッ
ドと前記半導体層とが互に絶縁されていることを特徴と
する半導体集積回路。 2、特許請求の範囲第1項記載の集積回路において、熱
酸化膜の厚さが0.3μm以上、気相成長酸化膜の厚さ
が0.2μr世メ上であることを特徴とする半導体集積
回路。
[Claims] 1) - Forming a semiconductor layer of opposite conductivity type including two bibor elements on a conductivity type semiconductor substrate, and fixing an electrode made of multiple metals on the main surface of the semiconductor substrate having the semiconductor layer. In a semiconductor integrated circuit provided with wiring pads, a thermal oxide film formed on the surface of the reverse conductivity type semiconductor layer and a vapor-phase grown semiconductor oxide film grown on the thermal oxide film form a bond between the wiring pads and the semiconductor layer. A semiconductor integrated circuit characterized in that layers are insulated from each other. 2. The integrated circuit according to claim 1, wherein the thermal oxide film has a thickness of 0.3 μm or more, and the vapor-grown oxide film has a thickness of 0.2 μm or more. integrated circuit.
JP57205645A 1982-11-24 1982-11-24 Semiconductor integrated circuit Pending JPS5994850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57205645A JPS5994850A (en) 1982-11-24 1982-11-24 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57205645A JPS5994850A (en) 1982-11-24 1982-11-24 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5994850A true JPS5994850A (en) 1984-05-31

Family

ID=16510318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57205645A Pending JPS5994850A (en) 1982-11-24 1982-11-24 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5994850A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120781A (en) * 1976-04-05 1977-10-11 Nec Corp Semiconductor device
JPS54128280A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Resin-sealed semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120781A (en) * 1976-04-05 1977-10-11 Nec Corp Semiconductor device
JPS54128280A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Resin-sealed semiconductor device

Similar Documents

Publication Publication Date Title
US3952404A (en) Beam lead formation method
US5342806A (en) Method for fabricating a semiconductor device having a conductor structure with a plated layer
US4042954A (en) Method for forming gang bonding bumps on integrated circuit semiconductor devices
US4495222A (en) Metallization means and method for high temperature applications
JPS5994850A (en) Semiconductor integrated circuit
JP3349656B2 (en) Bump and manufacturing method thereof
JPS59213145A (en) Semiconductor device and manufacture thereof
JPS5994851A (en) Manufacture of semiconductor integrated circuit
JPH02224336A (en) Manufacture of semiconductor device
JPS60262443A (en) Forming method of multilayer interconnection
JPH05291186A (en) Formation of metal contact on surface of semiconductor chip
JPH0697663B2 (en) Method for manufacturing semiconductor device
JPS63127550A (en) Manufacture of semiconductor device
JPS5823940B2 (en) Electrode formation method for semiconductor devices
JPS5984468A (en) Semiconductor device
JPS59229866A (en) Semiconductor device
JPH0394451A (en) Wiring structure of semiconductor device
JPH03268385A (en) Solder bump and manufacture thereof
JPH07130790A (en) Construction of electrode of semiconductor device
JPH01215033A (en) Bonding pad for semiconductor chip
JPS58134428A (en) Manufacture of semiconductor device
JPS6127677A (en) Manufacture of semiconductor device
JPS62281356A (en) Manufacture of semiconductor device
JPH04162531A (en) Manufacture of semiconductor device
JPS5933850A (en) Manufacture of semiconductor device