JPS5994850A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the insulating performance of an oxide Si film preventing an electrode comprising multiple metallic layer from producing a defect such as discontinuity etc. by a method wherein, in a semiconductor integrated circuit containing bipolar elements, a vapor grown oxide Si film is deposited on a thermal oxide film on the surface of an Si layer. CONSTITUTION:An aluminum wiring 11 is provided on a P type Si substrate 1 with an N type epitaxial Si layer 4 without performing separated diffusion through the intermediary of an oxide Si film 5 produced by heat-treatment under high temperature oxidative atmosphere and another oxide Si film 18 deposited by chemical vapor growing process and after providing a nitride Si film 12 coated by vapor growing process with an opening, a bump electrode comprising an Cr film 13, a Cu film 14, an Ni film 15 and an Sn-Pb solder alloy layer 16 is formed. Through these procedures, any step difference due to formation of the separated diffusion layer may be eliminated because any separated diffusion layer need not be formed at all since the shortcircuit between a wiring and transistor elements due to pinholes in the oxide Si film 5 is restrained by means of depositing the vapor grown oxide Si film 18 to improve the insulating performance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor integrated circuit including a bipolar element, and particularly in a semiconductor integrated circuit in which a wiring pad portion (an electrode made of two or more metal layers) is formed.

The manufacturing method normally carried out in semiconductor integrated circuits including bipolar elements will be explained by illustrating the manufacturing steps in Part 1) to A). A window is opened by forming the Si oxide film 2 for the first time and photo etching (first time). Next, a shallow diffusion Jso 3 of the n+ buried layer is formed (FIG. 1b)). After the oxidized Sii 2 is once removed, an n-type Si layer 4 is formed on the surface of the Si substrate 1 by epitaxial growth (first time). By the second formation of the oxidized S1 film 5 and photoetching, a window is opened for p-type impurity diffusion to form mutually separated n-type regions (first time). The p-type isolation diffusion layer 6 is formed to be sufficiently deeper than the n-type epitaxial growth layer 4 (first time). A third photo-etching process is used to open a window in the oxide S1 film 5 so that an npn transistor is formed in the isolation region having the nM-containing layer, and a pace expansion layer 7 is provided (FIG. 1f))
. Next, in the fourth photoetching step, the Si oxide film 5
After opening a window, shallow diffusion of n is performed to form a transistor diffusion layer 8 and a collector diffusion layer 9 (npn') (Fig. 1g).
). The fifth photoetching process removes n and p.
A window for a terminal is made in the area for making an ohmic contact for wiring, and an AI layer 10 is deposited with pure nitrogen over the entire main surface of the Si substrate 1 (FIG. 1h)). By the sixth photo-etching step, the wiring of the AI layer 10 is completed, and the main part of the Ueno process is completed (Fig. ii 41 i)).

FIG. 2 shows an example of the structure of the wiring pad portion and the bump electrode formed on the surface of the isolation region surrounded by the isolation diffusion layer 6 by the conventional manufacturing method as described above.

In Figure 82, an Or film 13 and an Ou film 1 are formed on the surface after selectively removing the phosphorized 8i film 12 that has adhered to the aluminum wiring pad portion 11.
4. and INi film 15 are deposited in this order, with the top layer being 5
It shows a structure in which a bang electrode is plated with n-Pb solder alloy. If a pinhole or the like exists in the Si oxide group 5 formed between the 'α pole made of multiple metal layers and the semiconductor surface, the current flowing into the semiconductor from the electrode may affect the operation of the transistor. This is provided to prevent any influence from occurring.

However, if pinholes or the like exist in the Si oxide film 5 formed between the electrode made of multiple metal layers and the semiconductor surface, not only will the insulation performance be impaired, but the performance of the chip Attempting to reduce the size also causes the following structural problems. That is, FIG. 3 shows OrN 13 , Ou film 14 , Ni film 15 and 5n
- The wiring pad portion with the bang electrode made of multiple metal layers of the Pbi solder alloy layer 16 extends within the curve of the isolation region surrounded by the isolation diffusion layer 6 (limited to above the distribution diffusion layer 6). Similar examples include cases where the wiring pad part jumps over the isolation diffusion layer 6 and extends into the isolation region that is in momentary contact, or where the wiring pad part is used as a circuit resistor due to layout constraints such as wiring. In some cases, the impurity diffusion layer 6 or the impurity diffusion layer (not shown) is selectively diffused when providing the separation diffusion layer 6 or an impurity diffusion layer (not shown). , it is inevitable that a step will be formed in the Si oxide film 5 under the wiring band portion. FIG. 4 shows a partial example of a defect in which the multi-metal layers become discontinuous at the step portion when a bump electrode made of multiple metal layers is formed on the Si substrate 5 with a step difference. This is an enlarged illustration. The possible cause of this defect is the Si oxide film 5.
In contrast, electrodes made of multiple metal layers generally require a layer of Or, Ou, and Ni, which is the base metal, to avoid wrinkles caused by thermal expansion. Thickness 0.5μ each
Since the thickness is often less than m, if there is a dimensional difference of this degree, the underlying metal will not be sufficiently coated at the stepped portion.

FIG. 4 shows the Or film 13. This clearly shows that the coating of the Ou film 14 is cut off at the step portion. If this ridge defect occurs, the etching solution may enter and erode the electrode during the electrode formation process, resulting in an open defect due to breakage of the aluminum wiring. Part 5) to f) show the steps of manufacturing bump electrodes by repeating the photo-etching process in the order of steps, and step C)
Then, the Or film 13° and the Ou film 14 are deposited, and in step d) the Ou film 14 is deposited.
However, if the above defects exist, the underlying Or film 13 will be etched during etching.
It may even erode. The same thing is in step e.
) can also occur in the case of the nickel film 15 and solder plating layer 16. Note that 17 represents a photoresist. If the underlying metal of the electrode is eroded in this way, a problem arises in that plating cannot be applied in the final electroplating process.

It is an object of the present invention to provide a semiconductor integrated circuit in which electrodes are formed without causing defects such as continuous parts.

In the present invention, a thermal oxide film on the surface of an epitaxial Si layer is further vapor-phased by separating diffusion generally used in semiconductor integrated circuits including bipolar elements.

Since FIG. 6 shows an embodiment of the present invention, the same reference numerals and names as in FIGS. 1 to 4 are used.

According to the present invention, in FIG. 6, an n-type epitaxial gill Si layer 45: an aluminum wiring 11 is formed through a 0.2 μm 8 degree Si oxide film 18 on which isolation diffusion is accumulated on the p-type Si substrate 1. After opening the Si nitride film 125 deposited on it by vapor phase epitaxy, Or, [13,0ui
1114. A bump electrode is formed of a Ni film 15 and a 5n-Pb solder alloy layer 16.

In this configuration, vapor phase growth oxide st is formed on the oxide S1 film 5.
The reason why the film IS is laminated is to reinforce the 8i oxide film and prevent a short circuit between the electrode and a functional element such as a transistor when a pinhole exists in the Si oxide film. As shown by the white side of the relationship between the S1 oxide film thickness and the pinhole density in Figure 7, if the Si oxide film 5 is used alone, there will be no pinholes when the film thickness is 0.7 μm or less, and impurity diffusion will occur. Even if the film thickness becomes 1 μm or more by repeating the process again, new pinholes may occur, so 02
The problem of pinholes has been solved by depositing a vapor phase grown Si oxide film 18 with a thickness of .mu.m or more. Further, the coatings of the modified example shown in FIG. 6 can also be used in combination.

As explained above, according to the present invention, a vapor-grown 8i thin film is deposited on a Si oxide film to suppress short-circuits between wiring parts and transistor elements due to pinholes, and to improve insulation performance. Therefore, there is no fear that defects will occur in the magnetic pole base metal in the wiring pad portion due to the step difference in the oxide film caused by the formation of the isolation diffusion layer. Further, according to 1, it is also possible to provide a wiring pad portion on a shallowly diffused diffusion resistor. As described above, the present invention not only simplifies the manufacturing process of semiconductor integrated circuits including bipolar elements, but also greatly contributes to improving reliability.

In addition, the present invention is applicable not only to the formation of bump electrodes as described above, but also to the formation of wiring pads with electrodes made of multiple metal layers such as beam lead structures. It can also be applied to improving membranes. In addition, it can also be applied to the case where wiring pads are installed on functional elements.

[Brief explanation of the drawing]

Figures 1 a) to i) are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit, Figures 2 and 3 are cross-sectional views showing a conventional bump' electrode structure, and Figure 4 shows defects in the panda electrode. Expanded cross-sectional views, FIGS. 5a) to 5D are cross-sectional views showing the manufacturing process 8 of the bump' electrode, FIG. 6 is a cross-sectional view showing the bump electrode according to the embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the silicon oxide film and the pin. FIG. 3 is a diagram showing the relationship between hole densities. P-type Si substrate, 2.5: mSr film, 4: n-type nitride seven-layer Si layer, 6: isolation diffusion layer, 11: AI wiring pad, 12: Si nitride film, 13: Or film, 14: Cu film,
15m+'lt film, 15:5n-Pb solder alloy layer, 1
8: Vapor-phase grown Si oxide film. lf'l Mouth T 2 Mouth T3 Mouth Sai 4 Mouth/4 years old! 50 T 6 figure

Claims (1)

[Claims] 1) - Forming a semiconductor layer of opposite conductivity type including two bibor elements on a conductivity type semiconductor substrate, and fixing an electrode made of multiple metals on the main surface of the semiconductor substrate having the semiconductor layer. In a semiconductor integrated circuit provided with wiring pads, a thermal oxide film formed on the surface of the reverse conductivity type semiconductor layer and a vapor-phase grown semiconductor oxide film grown on the thermal oxide film form a bond between the wiring pads and the semiconductor layer. A semiconductor integrated circuit characterized in that layers are insulated from each other. 2. The integrated circuit according to claim 1, wherein the thermal oxide film has a thickness of 0.3 μm or more, and the vapor-grown oxide film has a thickness of 0.2 μm or more. integrated circuit.