JPS5886743A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5886743A
JPS5886743A JP56185864A JP18586481A JPS5886743A JP S5886743 A JPS5886743 A JP S5886743A JP 56185864 A JP56185864 A JP 56185864A JP 18586481 A JP18586481 A JP 18586481A JP S5886743 A JPS5886743 A JP S5886743A
Authority
JP
Japan
Prior art keywords
solder
layer
substrate
pellets
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56185864A
Other languages
Japanese (ja)
Other versions
JPH0218584B2 (en
Inventor
Iwao Matsushima
松島 巖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP56185864A priority Critical patent/JPS5886743A/en
Publication of JPS5886743A publication Critical patent/JPS5886743A/en
Publication of JPH0218584B2 publication Critical patent/JPH0218584B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE:To separate a substrate into pellets in good yield by melting the solder electrode layer of the back surface of the substrate along a pattern, simultaneously attracting, removing the layer to expose the back surface electrode in a lattice shape and cutting the substrate. CONSTITUTION:A laser light 7 having the prescribed width is emitted from the emission port 6 of a laser generator onto a solder layer 3. A glass attracting tube 8 of conical shape is mounted on the end of the port 6, thereby communicating with a suction pump through a branch tube 8a and a tube 9. An in-desk base which places the laser generator or a substrate 1 is moved to move the aiming point of the light 6 along the scribing line 5 of the lattice pattern of the substrate 1, and the layer 3 is attracted and removed from the port 8b while melting the layer 3. In this manner, the solder can be readily removed, no clogging of a dicing blade occurs in case of separating the pellets, the separation can be facilitated, and no improper breakage occurs.

Description

【発明の詳細な説明】 この発明に、−問4極上に半田層を形成し次半4体装−
の’J yta 7f汲に関するものである。
[Detailed Description of the Invention] In this invention, a solder layer is formed on the top of the fourth layer and the next half is mounted.
This is related to 'J yta 7f pump.

半導体ペレットをろう付けによってステムやリードフレ
ームにマクントする場合、溶−半田上にペレツ)2押し
付ける万人では、gIIIK半田表1編に数比や7ラツ
クスV浮き出しによる表面屓がte成さnて接信t−4
するので、Cルを破壊する之めの操作が必要となって生
産性が悪化する@そこで、ペレットの哀L1[l電礪上
に予め半田層t trap を況しておさ、これtマク
ント圓に当接した状・誦で半田−を別f@溶1してマク
ントするペレット予備半田法と称される1犬が考えられ
ている。
When attaching semiconductor pellets to a stem or lead frame by brazing, most people who press the pellets onto the molten solder will not have surface ridges due to the numerical ratio or 7 lux V embossment in the gIIIK solder table 1. contact t-4
Therefore, an operation to destroy the C is required, which deteriorates productivity. A method called the pellet pre-soldering method has been considered, in which the solder is melted separately in the state of contact.

と仁ろが、このようなペレットを得るために分−曲の半
導体クエーハに半田層を形成すると、半田層が軟らかく
且つ比較的厚み勿・目°することに起因して、半導体ク
エーハ會格子状にX1Uしテヘレットに分離するとき、
切断用のダイシンググレードに目aまりを生じて切断が
1.11遜となり易く、また半導体クエーハの表ui+
1lllから区割−に沿って途中まで!4?を杉1況し
て破断する方法でも半田層部で4R所面が不揃いとなっ
ていわゆるアベック不良を生じ易い。−万、これ金24
犬する友めに半辱体りエーハの区割ナベき分Iv!l−
に沿って半田層の存在しない部分を形成する方決が提呆
されているが、この方決は一面題憾のオー4yり金属と
半4体の例えばシリコンとの半田に対する。−九性の差
を利用してシリコン品にtべ融半田が付行しないように
す0ものである几め、オーミック盆Y4を非常に王政の
多い4真峠刻去で格子状にエツチング除去して/ぐター
ン化する必要゛があり、時間的な損失が大きく、材料面
からもコスト−となる〇 この発明は、上記従来の欠I:Lを改善すること全目的
としており、半導体クエーハの誕l電極側の全面に所定
・・Jみの半田層を形成した波、ペレットに区割する。
When a solder layer is formed on a semicircular semiconductor wafer to obtain such pellets, the solder layer is soft and relatively thick, so the semiconductor wafer has a lattice shape. When X1U is separated into Teheret,
The dicing grade used for cutting tends to become clogged and the cutting becomes inferior to 1.11, and the surface of semiconductor wafer ui+
From 1llll to halfway along the division! 4? Even with the method of breaking the cedar in one state, the 4R planes in the solder layer portion are likely to be uneven, resulting in so-called avec defects. - 10,000, this is 24 gold.
Eha's half-humiliated dog friend's division IV! l-
A solution has been proposed to form a portion along which no solder layer exists, but this solution is one of the problems with soldering between metal and half-metal, for example silicon. -Using the difference in nineness to prevent T-beam solder from adhering to silicon products, we removed the ohmic tray Y4 by etching it in a lattice pattern with the very common 4-toge carving process. This invention is aimed at improving the above-mentioned conventional deficiencies, and it is necessary to turn the semiconductor After forming a solder layer of a predetermined length on the entire surface of the electrode side, the wave is divided into pellets.

1v!1子状パターンに唱って半田mt溶融させると共
に、この石−した半田を吸引除去することにより、格子
状に轟面′−蝋t−露出させ、この後上記透出した成U
kJ−極から半導体クエーハを切断してペレットに分−
することt待機とする半導体装−の製造方法に保る〇以
下、この発明の方法を図面によって説明すれば、筐ず、
第7図で示すように半導体クエーハfilO娯面側のオ
ーミック金Tl4−からなるII&面4極(21の表面
に、Pfr定)4みて半田層(3]を形成する。図中(
4)は区割すべ!ペレット単位を示し、このペレット単
位(4)はそれぞれ目的とする半導体素子単位を含んで
おり、ま友ペレット単位(4)の区割線(5)は格子状
パターンとなっている。次に、上記半田層(3)t−区
割線(5)に沿って所定幅で溶融させ、直後に溶融半田
を吸引除去し、第一図で示すように表面′4極(21表
面をih子状に4出させる・その後、上記格子状パター
ンの4出した邊面電極から′@矢に準じて切断し、第3
図で示すようなペレット単位(4)に分離する〇上述の
ように半田層13)全格子状パターンで溶融除去する手
段は葎々存在するが、待にだ融手段と吸引除去手吹とが
一体化された装置の便用が好適であり、以下その笑II
例全図面に従って説明する。
1v! By melting the solder mt in a lattice-like pattern and removing it by suction, the wax surface is exposed in a lattice pattern, and then the transparent solder is removed.
Cut the semiconductor wafer from the kJ-pole and divide it into pellets.
〇The method of the present invention will be explained below with reference to the drawings.
As shown in FIG. 7, a solder layer (3) is formed on the surface of the semiconductor wafer filO made of ohmic gold Tl4- (21) with a constant Pfr.
4) should be divided into sections! The pellet units (4) each include a target semiconductor element unit, and the division lines (5) of the Matomo pellet units (4) are in a grid pattern. Next, the solder layer (3) is melted in a predetermined width along the t-dividing line (5), and the molten solder is immediately removed by suction, and the surface '4 pole (21 surface is・After that, cut the 4 side electrodes of the grid pattern according to the '@ arrows, and make the 3rd
Separating into pellet units (4) as shown in the figure 〇 As mentioned above, there are methods for melting and removing the entire solder layer 13) in a lattice pattern. The convenience of an integrated device is preferred, hereinafter referred to as II.
An example will be explained with reference to all the drawings.

逼り図は半田層(3)の溶1戚にレーザ光を利用する例
である。図において、(6)はレーデ発生装置(図示幡
)のレーデ光照射口であり、(7)は半11]゛m i
l+上で所定・鴎と、tΦよつに礒ったレーデ光金示す
。このレーデ光照射口(6)先−Vこは通例な石英また
は〃゛ラス杉成さルたj1fIA杉の吸引α(8)が装
着されている。この吸引管(8)は枝管(8a)でドレ
ーンタンク付きの吸引ポンプ(図示略)とチューブ(9
)k介して4繍しており、また先端のレーデ光(7)の
黒革に一致する位置に半田吸引口(8b)2備えている
。この装置i!を夏用する場合、レーデ光(7)の照′
14点が半4体りエー/%111の格子状パターンの区
ill liM ti)に沿うようにレーデ発生装置1
側もしくは半4体りエーハIll t−滅せたインデッ
クステーブル(図示略)ラボ幼させ、半!B層fat 
t−レーザ光(7)で溶、aさせつつ半田吸引口(8b
)より溶融半田を吸引除去する。
The diagram shows an example in which laser light is used to melt the solder layer (3). In the figure, (6) is the radar light irradiation port of the radar generator (illustration flag), and (7) is the half 11] mm i
On l+, the specified seaweed and the rede light gold sprinkled on tΦyotsu are shown. A suction α (8) made of conventional quartz or lath cedar is attached to the tip of this radar light irradiation port (6). This suction pipe (8) is a branch pipe (8a) that includes a suction pump with a drain tank (not shown) and a tube (9).
) K is sewn through 4 stitches, and a solder suction port (8b) 2 is provided at a position corresponding to the black leather of the lede light (7) at the tip. This device i! When using in the summer, the light of Rede light (7)
The radar generator 1 is placed so that the 14 points are along the sections of the grid pattern of half 4 pieces/%111.
Side or half 4 bodies Eha Ill t-extinct index table (not shown) lab young, half! B layer fat
While melting with the T-laser beam (7), open the solder suction port (8b).
) to remove the molten solder by suction.

@j図で示すズ施例は、半田d i31の溶融にヒータ
を利用するものである。aj図において、1101は’
la@ (IOIL)が尖り九形状金有する半田とて形
ヒータであり、先端(10亀)に開口(lot)) 1
備え、先4(10a)との接触で生じただ融半田を開口
(lot))からヒータHOI内部に設けられた通路(
10a )とこれに連結するチューブ(ロ)全通して吸
引除去するよ′うに構成されている。g融点の移−1は
、@1111al4にヒータUυもしくは半導体クエー
ハ111のステージ(図示略)t−動作して行なう。
The embodiment shown in figure @j uses a heater to melt the solder di31. In the aj diagram, 1101 is '
la @ (IOIL) is a solder lever-shaped heater with a pointed nine-shaped metal, and an opening (lot) at the tip (10 tortoise)) 1
In addition, the melted solder generated by contact with tip 4 (10a) is passed from the opening (lot) to the passage (lot) provided inside the heater HOI.
10a) and the tube (b) connected thereto are constructed so as to be removed by suction. The transition (1) of the melting point is performed by operating the heater Uυ or the stage (not shown) of the semiconductor wafer 111 at @1111al4.

第5図で示す実施例は、第5図の例と同様にヒータを利
用するものであるが、ヒータ+121は格子状パター2
ンの区割線(5)の/ラインに引当する部分の半田層(
3)を一時に溶融するように横長の先端(12a)全存
しており、溶融半田は同様に先端(12a)に形成され
たスリット状開口(]、2t)) jり内部のAWI(
120)とチューブns2通して吸引除去される。
The embodiment shown in FIG. 5 uses a heater like the example in FIG.
The solder layer (
3) The oblong tip (12a) is completely present so as to melt the solder at once, and the molten solder also flows through the slit-shaped opening (], 2t)) formed at the tip (12a).
120) and is removed by suction through tube ns2.

なお、この発明において、溶111!II除去する半田
層(33の4は半導体装櫂の設計によって決まるが、通
常50〜600μの1lli!囲である口重上のように
、この発明の方法によれば、半4体りエーハの嬌面電極
側に形成した半田層tペレットに区割する格子状パター
ンに沿って極めて容易に除去できるため、半導体クエー
ハヲペレットに分−する祿、グイシンググレードに11
りを生じたり、破断でアベックイ遺、を生じることがな
く、分離が非常にd)Aとなり、その結果として裏面に
半田層全形成した半導体装置をdMiかつ安価に提供で
きる。
In addition, in this invention, melt 111! According to the method of the present invention, the solder layer to be removed (4 in 33 is determined by the design of the semiconductor package, but is usually 50 to 600 μm in diameter). Since the solder layer formed on the side electrode side can be removed extremely easily along the grid pattern that divides the semiconductor quadrature into pellets, it is difficult to remove the solder layer formed on the surface electrode side.
Separation is very d) A without causing cracking or damage due to breakage, and as a result, a semiconductor device with a solder layer entirely formed on the back side can be provided at low cost and with dMi.

【図面の簡単な説明】[Brief explanation of the drawing]

石/図乃至1263凶はこの発明の半導体%瀘の製造方
法を工程順に示し、第7図Fi裏面全面に半田層を形成
した牛4体りエーハの断rTJ図、第2図は区I!ll
線に沿って半田層ram除去した半導体クエーハの断面
図、1g3図は半導体クエーハより分噛し之ペレットの
断面図であQ、%グ図乃至第6図はいずれもこの発明の
実施例における半田層の溶融除去工部を示す斜視図であ
る11)・・半導体クエーハ、(2)・・戚面電極、(
11・・半田層、(4)・・ベレット単位、(!I)・
・格子状パターンの区割線。 第1図 県−2図 薯3 闇
Stone/Figures to 1263 show the manufacturing method of the semiconductor % filter of this invention in the order of steps, and Figure 7 is a cross section rTJ diagram of a four-body Aha with a solder layer formed on the entire back surface, and Figure 2 is a section I! ll
A cross-sectional view of the semiconductor quafer from which the solder layer RAM has been removed along the line, Figure 1g3 is a cross-sectional view of a pellet separated from the semiconductor quafer, and Figures Q, %g to Figure 6 all show the solder in the embodiment of this invention. It is a perspective view showing the melting and removal process of the layer 11)... semiconductor wafer, (2)... relative surface electrode, (
11...Solder layer, (4)...Bellet unit, (!I)...
- Grid pattern dividing lines. Figure 1 Prefecture-2 Figure 3 Darkness

Claims (1)

【特許請求の範囲】[Claims] 11)  多数の^子t+V成した半導体クエー/〜の
に而゛4へ1側の全面に所定メ4みの半tll )m 
k形成した後、ペレットに区割する慢す子状パターンに
沿って半[ローtPfr疋e−で6融させると共に、こ
のrd、aシた半1+J i吸引除去して格子状に躾−
一−tkli露出させ、この便上記4出した一面゛4極
面から半導体クエーハC切断してペレットに分−するこ
とケ待頭とする半導体装置の製造万汲0
11) Semiconductor quay with a large number of children t+V/~, so ゛4 has a predetermined number of half tll on the entire surface of side 1)m
After forming the pellet, melt it with a low tPfr x 6 along the lattice-like pattern to divide it into pellets, and remove the rd, a and half 1 + J i by suction and train it in a grid pattern.
Manufacture of semiconductor devices by exposing semiconductor wafers and cutting the semiconductor wafer C from the quadrupole surface exposed in 4 above and separating it into pellets.
JP56185864A 1981-11-18 1981-11-18 Manufacture of semiconductor device Granted JPS5886743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56185864A JPS5886743A (en) 1981-11-18 1981-11-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56185864A JPS5886743A (en) 1981-11-18 1981-11-18 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5886743A true JPS5886743A (en) 1983-05-24
JPH0218584B2 JPH0218584B2 (en) 1990-04-26

Family

ID=16178212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56185864A Granted JPS5886743A (en) 1981-11-18 1981-11-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5886743A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100514099B1 (en) * 1998-12-04 2005-11-25 삼성전자주식회사 Laser cutting device and cutting method
KR100543368B1 (en) * 1998-12-04 2006-05-12 삼성전자주식회사 Laser cutting equipment
JP2010182901A (en) * 2009-02-06 2010-08-19 Disco Abrasive Syst Ltd Method of dividing semiconductor wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017176A (en) * 1973-06-12 1975-02-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017176A (en) * 1973-06-12 1975-02-22

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100514099B1 (en) * 1998-12-04 2005-11-25 삼성전자주식회사 Laser cutting device and cutting method
KR100543368B1 (en) * 1998-12-04 2006-05-12 삼성전자주식회사 Laser cutting equipment
JP2010182901A (en) * 2009-02-06 2010-08-19 Disco Abrasive Syst Ltd Method of dividing semiconductor wafer

Also Published As

Publication number Publication date
JPH0218584B2 (en) 1990-04-26

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