JPS5853857A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To make easy formation of substrate electrode window and prevent breakage of wiring by providing projected semiconductor substrate in the area where there is no oxide thick film and by providing the electrical elements to such projected surface and the electrode leading layer which gives a fixed potential to the substrate. CONSTITUTION:An Si3N4 mask 22 is provided over the SiO2 thin film 21 of the p type Si 11, then the B ions are implanted thereto, the p<+> layer is formed. Thenm the Si3N4 mask 24 is coated again. Thereafter, it is heated in the oxide film 12 is selectively formed. The masks 24, 22 and SiO2 film 21 in the region 11 are selectively removed, and the surface is newly covered with the oxide thin film 26. Succeedingly, the poly-Si gata electrode 28 and gate oxide film 26 are provided and the N layer 16 is formed by diffusion of phosphorus P. Next, the mask 24 on the region 25 is removed and the surface is covered with the thermal oxide film 29. Thereafter, an aperture is opened like an existing device and the Al electrode 20 is provided thereto. Thickness of the SiO2 film is almost the same in the region 11 and 27, each electrode window can be opened by the same process and is 1/2 or less than the field oxide film. Therefore, breakage of wiring does not occur at the window part. In addition, the power supply voltage can be applied to the substrate on the substrate surface and thereby operation speed of IC can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing MI8 integrated circuits.
Figure 1 relates to a method for forming a so-called contact area, which is a region for applying a power supply voltage to a substrate of an MO & integrated circuit (particularly 8i game), which is formed using a conventional method.
This is a cross-sectional view of the transistor region and its surrounding area l of a channel type 8i (channel type 8i game) MO8 integrated circuit. The surrounding area is thick (~l
j1m) A thin (~1000λ) II gate oxide film 13 is formed on a part of the Pfi8i substrate 10fi surface of the o-transistor region 11 recessed by the field oxide film 12, and the surface of the gate oxide 11113 is made of NW polycrystalline Si. It is covered with a gate electrode 14 (4 to 0.5 μm). The Si surface under the gate oxide film 13 is a channel region 15 . Transistor region 11 (excluding channel region 15), KaNI18i region 16) forming the source and drain of the transistor, and a P-type substrate l on the silicon surface under field oxide film 12.
A P-type Si layer 17 having an impurity concentration higher than that of O is formed. The surface of the transistor region 11 ON layer 8i region 16 and the surface of the N-type polycrystalline Si gate electrode 14 are relatively thin (30
00 to 5000^)/8i It is covered with a pseudo film 18, and a contact hole 19 is formed in a part of the film 4B, which penetrates to the surface of the NW8i region 16 and the surface of the N-type polycrystalline 8i gate electrode 14. M layer 20 for wiring
(thickness ~1.2 μm) is connected to the surface of the N type 8i region 16 and the surface of the Δ type crystal Si gate electrode 14 through this contact hole 19.

As is clear from Fig. M1, in the N-channel type 8i MO8 integrated circuit formed by the conventional method,
Power is applied to keep the i-substrate 10 at a constant potential not from the front surface where the transistor region 11 is formed, but from the back surface. This is P type 8
Since the high impurity concentration P i8i $ 17 on the thorny surface of the i-substrate 10 is under the thick field oxide film 12 of ~l-μm, the Sin1m1g on the surface of the hemiform 8i region 16 and the surface of the N-type polycrystalline 8i gate electrode 14 is It is extremely difficult to simultaneously make contact holes for the substrate in the field oxide film 12 during the process of making the contact holes 19 in the field oxide film 12. This is because #1 is almost impossible to connect to the surface of the P-type 81 region 16.

That is, in the conventional method, the ON surface of the P-type 8i substrate 1 is made of a thin (~500A) 8i0. After covering with membrane, add 1 more
- Cover with a silicon nitride film with a thickness of ~100 OA, and selectively remove the silicon nitride film using photoresist technology so that only the silicon nitride film that covers the portion that will later become the transistor region 11 remains;
P is added to the surface of the P-type 8i substrate lO from which the silicon nitride film has been removed.
Since a thick field oxide film 12 (~IAm) is formed by thermal oxidation after introducing a type impurity (for example, -g), it is difficult to form a contact hole for the substrate. Therefore, the distance from the substrate power supply point to the active region is 1L, which is the thickness of the substrate ~400μm).
Since the series resistance increases, the operating speed decreases.

Further, the self-attachment of the integrated circuit pellet to the support must be carried out using a fixing material that allows for one-sided contact.

It is an object of the present invention to eliminate the above-mentioned difficulties associated with substrate contact drilling that occur when MO8 integrated circuits are formed using conventional methods, and to provide a substrate contact hole that can be formed in the same step as contact holes for source/drain regions and gate electrodes. This provides a structure in which contact holes can be easily drilled, and the A wiring does not break at the large end of the contact. This is a diagram explaining the manufacturing method.The main surface of the OP type 84 substrate IO surface is thermally oxidized to form a thin 8 i 0. After forming the film 21, a first silicon nitride film 22 having a thickness of about 10-00 Å is deposited by CVD.

The first silicon nitride film except on the transistor region ll is removed by photolithography (FIG. Jl).

Next, using the photoresist layer 23 and the first silicon oxide film 22 as an i layer, boron is selectively introduced into the region where the first silicon oxide film has been removed.
A P-type 8i region 16 having an impurity concentration higher than that of the substrate 10 is selectively formed on the surface of the substrate 10 (FIG. b). The photoresist layer 23 is removed in the same manner as the conventional method up to the depth, and a second silicon nitride film 24 with a thickness of about 10,001 mm is formed.
After depositing, the second silicon nitride film 24 except on the first silicon nitride film 22 on the transistor region 11 and on the substrate contact region 25 is selectively removed using photolithography technology (Figure C). , the pstalomide film 22 and the second nitride film 2 are heated in an oxidizing atmosphere.
Selectively oxidize the parts not covered by 4 to form a thick field oxide 1i1[12 of 171 m 8 degrees (Figure d)
Free transistor region l is created using zero-order photolithography technology.
second silicon nitride film 24, first silicon nitride film 22.
and 8i0 stroma 21 was removed, and thermal oxidation
8i false j[26 with a thickness of 1000λ is formed on the transistor region 11 (Fig. The polycrystalline 8i film is removed leaving only the gate electrode part 28, and the exposed S5 pseudo film 2 is removed by
After removing 6, by ion implantation method or thermal diffusion method)
Phosphorus is introduced into the polycrystalline silicon gate electrode 28 and the exposed transistor region 11.

A hexagonal Si region 16 is formed (FIG. f). At this time, since the substrate contact region 25 is covered with the second silicon nitride film 24, phosphorus is not introduced. Next, by removing the silicon nitride film 24 on the Ks substrate contact region 25 and performing thermal oxidation, the transistor region 11. On the polycrystalline silicon gate electrode 28 and substrate contact region 25, 8i0. A film 29 is formed (FIG. 9).

Thereafter, a contact hole is formed, an AI film for wiring is deposited, etc. in the same manner as in the conventional method, thereby obtaining a channel @8i transistor having the structure shown in FIG.

As is clear from the above explanation, according to the two inventions,
A film 8i0 covering the substrate contact region 25 and a film 8i0 covering the transistor region 11 and the polysilicon gate electrode 28. Since it has a thickness approximately equal to that of the Siθ film, it is possible to easily form contact holes in the substrate in the same process as forming contact holes for the source/drain regions and gate electrodes. Since the thickness of the film is about 100% compared to the field oxide film, disconnection of the AI wiring at the large end of the contact will not occur. In an integrated circuit composed of a group of Si-gate Mθ8 transistors, the power supply potential is applied to the substrate using a Si-gate Mθ8 transistor group.
NO8) 7 It becomes possible to perform the process on the surface where the transistor group is formed, improving the operating speed of the integrated circuit, and further increasing the degree of freedom in the method of fixing the integrated circuit pellet to the support. is clear.

In addition, in the explanation above, N-channel type Si game)
NO8) A transistor was used, but even if the channel type is P type, the gate electrode material is also different.

High point metal such as W, dove, or WS, Mo8i.

It is clear that the effects of the present invention can be obtained even with silicides made of high melting point metals such as. In addition, as a semiconductor element, N
It is clear that in addition to 08 field effect transistors, bipolar transistors can also be used.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of an h-channel NO8 integrated circuit formed by a conventional method. FIG. 2 shows an N-channel type 8i according to an embodiment of the present invention.
Figure 3 is a partial cross-sectional view showing the process of forming an NO8 integrated circuit, and Figures (am) to (to) are partial cross-sectional views at each step. 1 is a partial cross-sectional view of a channel-type NO8 integrated circuit; FIG. 10...P-type 8i substrate, 12--field oxide film, 13.26--gate oxide film & 14
．． 28-...Polycrystalline 8i gate electrode%16--N
Type 8i region. 17... High degree P type 8i region, 20---
-A j k! , ff8 layer, 25...Substrate contact area 0 channels 1 Figure/l Sheep 2 figure (α) 2nd opening (g) (C) 1/ Figure 4 5 Ce) <f>

Claims (1)

[Claims] A semiconductor substrate having a selectively thick oxide film on its surface. The surface of the semiconductor substrate in the portion not having the thick oxide film protrudes from the surface of the semiconductor substrate below the portion having the thick oxide film), and a fixed potential is applied to the surface of the protruding conductor substrate between the EiliK electric element and the semiconductor substrate. What is claimed is: 1. An integrated circuit device characterized in that an electrode extension portion is formed to provide an electrode expansion portion.