JPS5852864A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5852864A JPS5852864A JP15117181A JP15117181A JPS5852864A JP S5852864 A JPS5852864 A JP S5852864A JP 15117181 A JP15117181 A JP 15117181A JP 15117181 A JP15117181 A JP 15117181A JP S5852864 A JPS5852864 A JP S5852864A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- transparent substrate
- integrated circuit
- semiconductor integrated
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路Ｃ以下略してＩＣ吉曹〈）チッ
プの透明基板上への実装に関する。さらに本発明け、透
明基板を用いたＩＯチップのフェイスダウンボンディン
グの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to mounting a semiconductor integrated circuit (hereinafter abbreviated as IC Kichiso) chip on a transparent substrate. Furthermore, the present invention relates to a face-down bonding structure of an IO chip using a transparent substrate.
近年、工０の発展は目を見けるものがあり、コンピュー
ターを始めとして家電製品においても、伺らかの形でＩ
Ｃが使われているのか現状である。In recent years, the development of industrial technology has been remarkable, and I/O technology has been increasing in various ways in computers and other home appliances.
The current situation is whether C is being used.
ＩＣの生産量が増加するに伴ってＩＣのコストはラーニ
ングカーブに従って低下して来ているのに約し、ＩＣの
実装コストは依然高い比率を占めてお抄、ＩＣの実装コ
ストの低減か大きな課題であった。Although the cost of IC has been decreasing according to the learning curve as the production volume of IC has increased, the cost of implementing IC still accounts for a high proportion. It was a challenge.
ＩＣの実装の中でもいわゆる第一実装階層と言われるＩ
Ｃチップのボンディングエ穆ハ、今日までワイヤボンデ
ィング方式、テープキャリア方式フリップチップのフェ
イスダウンボンディング方式郷があり、それぞれの長所
短所を生かした形で実用化されているのが現状である。Among IC implementations, I is said to be the so-called first implementation layer.
To date, there are wire bonding methods, tape carrier type flip chip bonding methods, and face-down bonding methods for C chips have been put into practical use by taking advantage of the advantages and disadvantages of each.
第１図はフリップチップを用いたフェイスダウンボンデ
ィングの説明図、第２図はプリップチップの構造を示し
ている。第１図中のＩＦ１基板、２は配線であり金属配
線が一般的に用いられる。３ｉｊ Ｉ Ｏチップであ！
＋４Ｆ！ポンディングパッドである。５はハンダである
。１に２図Ｆ！第１図で用いたＩＣチップの構造図であ
り、６はハンダバンプである。この様なフリップチップ
を用いたフェイスダウンボンディング方式は、他の２方
式と比較して、より多くのボンディング端子を一度にボ
ンディングすることが出来しかもボンディングに必要な
面積＃ｉ最も小さいきいう利点があるものの、ＩＣチッ
プ上にハンダバンプを形成しなＨればならずＩＣチップ
コストの増加が大きな問題であった。FIG. 1 is an explanatory diagram of face-down bonding using a flip chip, and FIG. 2 shows the structure of a flip chip. IF1 board and 2 in FIG. 1 are wiring, and metal wiring is generally used. With 3ij IO chip!
+4F! It is a pounding pad. 5 is solder. 2 figures F in 1! This is a structural diagram of the IC chip used in FIG. 1, and 6 is a solder bump. Compared to the other two methods, the face-down bonding method using such a flip chip has the advantage of being able to bond more bonding terminals at once and having the smallest area #i required for bonding. However, it is necessary to form solder bumps on the IC chip, and an increase in the cost of the IC chip is a major problem.
木兄明けかかる従来のＩＣチップのボンディング方式の
欠点を解決するために発明されたものであり、以下詳し
く説明する。It was invented in order to solve the drawbacks of the conventional IC chip bonding method, and will be explained in detail below.
第３図は本発明によるＩＣチップの基板へのボンディン
グ構造を示した図である。図中の７は透明基板、８け基
板表面上に形成された金−配線層、９けＩＣチップであ
る。１０け工０チップ十のポンディングパッドである。FIG. 3 is a diagram showing a bonding structure of an IC chip to a substrate according to the present invention. In the figure, 7 is a transparent substrate, 8 is a gold wiring layer formed on the surface of the substrate, and 9 is an IC chip. It is a 10-wire, 0-chip, 10-chip bonding pad.
このボンディングパーラドは、アルミニウムでもよいし
金でもよい、１１は本発明のｌｅ微である寒気伝導性を
有する感光性材料である。ＩＣチップのポンディングパ
ッドからこの感光性材料を介して基板上の配＃ＫＩ気的
に接続される。第４図は本発明で用いる透明基板上の金
属配線パターンを示す０図中の７と８は第３図中の番号
と対応している。オた図中のＡｔｊ、ボンディング後の
ＩＣチップの位置を示す想像線である。本発明によるＩ
Ｃチップのボンディング■程を第５図に示す、壇ず駆５
図（ａｌに示す様に、ガラス板あるいは石英板等の透明
基板上に金属層による配線１２を形成する。この配線は
、金属を＃着もしくにヌバッタ稜、ホトリングラフイー
にてパターニングしてもよいし、スクリーン印刷法にて
導体層を印刷後、焼成したものでもよい。その稜、第５
図（ｂ）の１３にて示す様に透明基板全面Ｋｌｌｌｌ導
伝導性する感光性材料の層を形成する。This bonding pad may be made of aluminum or gold, and 11 is a photosensitive material having cold conductivity, which is the material of the present invention. The bonding pad of the IC chip is electrically connected to the wiring board on the substrate via this photosensitive material. FIG. 4 shows a metal wiring pattern on a transparent substrate used in the present invention. 7 and 8 in FIG. 0 correspond to the numbers in FIG. 3. Atj in the figure is an imaginary line indicating the position of the IC chip after bonding. I according to the invention
The bonding process of the C chip is shown in Figure 5.
As shown in Figure (al), wiring 12 made of a metal layer is formed on a transparent substrate such as a glass plate or a quartz plate.This wiring is formed by patterning the metal with #deposit or Nubatta ridge using photolithography. Alternatively, the conductor layer may be printed using a screen printing method and then fired.
As shown at 13 in Figure (b), a layer of a photosensitive material having Kllll conductivity is formed on the entire surface of the transparent substrate.
この材料は例えば、導電性樹脂を含んだ感光性有機樹脂
（レジスト）でもよいし、また金属あるいけ炭素の微粉
末粒子を分散した感光性有機樹脂でもよい、さらＫこの
様な樹脂でなくても、光か当った所と肖らない所の電気
伝導性が異なる様な物質であってもよい、二わらの材料
は、透明基板とＩＣチップに対する接着力４大きい方が
望オしい。This material may be, for example, a photosensitive organic resin (resist) containing a conductive resin, or may be a photosensitive organic resin in which fine powder particles of metal or carbon are dispersed. Alternatively, it is preferable that the two-layer material has a high adhesion force 4 to the transparent substrate and the IC chip, which may be a substance that has different electrical conductivity in areas that are exposed to light and areas that are not exposed to light.
今、仮りに金属微粒子を分散させた感光性有機樹脂を例
にとって説明する。この有機樹脂は液体状−であり、透
明基板上への層の形ｒ！ｔ＃′ｉ例えばスピンナーコー
トにて行なう、その後第５図（ｃ）Ｋて示す如＜ＩＣチ
ップ１４をフェイスダウンの状態にて前記有機樹脂表面
上に押し当てた後、適当な温度、例えば８０〜１８０℃
の１１１度にてキュアし７ＩＱ４ツブを接着させる。そ
の後図中１５にて示す如く透明基板１１の裏面から光１
５を全面に照射する。この時、感光性有機樹脂がポジ系
であれば次の現像工程において、透明基板上の配線上の
樹脂層杖残ね、配線上以外の樹脂層は除去される。Now, explanation will be given by taking as an example a photosensitive organic resin in which fine metal particles are dispersed. This organic resin is in liquid form and can be deposited in the form of a layer on a transparent substrate. Then, as shown in FIG. 5(c)K, the IC chip 14 is pressed face down onto the organic resin surface, and then coated at an appropriate temperature, for example, 80°C. ~180℃
Cure at 111 degrees and adhere the 7IQ4 tubes. Thereafter, as shown at 15 in the figure, light 1 is emitted from the back surface of the transparent substrate 11.
Irradiate the entire surface with 5. At this time, if the photosensitive organic resin is positive, the remaining resin layer on the wiring on the transparent substrate and the resin layer other than on the wiring are removed in the next development step.
この状態を第５図（ｄ）に示す。図中の１６は配線上に
残された寒気伝導性を有する感光性材料である。This state is shown in FIG. 5(d). 16 in the figure is a photosensitive material having cold conductivity left on the wiring.
ＩＣチップと透明基板との接着性と、電気伝導性を増加
させるために１その後１００〜５００℃ノ温度でキュア
する。この様にしてＩＣチップのポンチインクは終了す
る。この本発明によるＩＣチップのボンディング方式の
特徴は、同時に多数のＩＣチップのボンディングが出来
ること、及びＩＣチップ上にバンプを必要としないこと
等である。Ｘ体的には、例えばポジレジスト中に金の微
粒子を混合したものを用い、る、透明基板及びＩＣチッ
プとの接着性を良くするために、その界面に接着剤の薄
い層を形成してもよい。ポジレジストは、キュアにより
体積収縮するために、電気伝導率けかな９増加する。In order to increase the adhesiveness between the IC chip and the transparent substrate and the electrical conductivity, it is then cured at a temperature of 100 to 500°C. In this way, punching ink on the IC chip is completed. The features of the IC chip bonding method according to the present invention include that a large number of IC chips can be bonded at the same time, and that no bumps are required on the IC chips. For example, a positive resist mixed with fine gold particles is used, and a thin layer of adhesive is formed at the interface to improve adhesion to the transparent substrate and IC chip. Good too. The electrical conductivity of the positive resist increases by a factor of 9 because the volume shrinks due to curing.
蒙６図は本発明による工０チップをボンディングした基
板を上から見た図であり、ｆた館７図は軸めから兄だ概
―図である０図中の１０は透明基板１３けＩＣチップ、
１６Ｆｉ電気伝導性を有する感光性材料である。館８図
は本発明にて用いるＩＣチップのポンディングパッド構
造を示す、館８図（＆）中の１７Ｖｉシリコン基板、１
Ｂは絶縁層、１９ｒゴアルミニウム層である。２０＃′
ｉパツジページ曹ン膜である。このアルミニウムパッド
は、接触の細軸性がやや低い。諏８図（ｂ）Ｆｉ、アル
ミニラムノくラド上に、クロム２１と金２２の２層を形
成したものであり、これを金パツドと言う、ノくラドの
表面が金の場合は、電気伝導性を有する感光性材料との
１気的接続の信頼性は非常に高い０本発明に用いるＩＣ
チップは第８図（ｃ） Ｋて示した様な／（ンプ２３か
付いたものでもよいことはいうまでもない。Figure 6 is a top view of the board to which the 0 chips of the present invention are bonded, and Figure 7 is an overview from the axis. chip,
It is a photosensitive material with 16Fi electrical conductivity. Figure 8 shows the bonding pad structure of the IC chip used in the present invention.
B is an insulating layer, a 19r goaluminum layer. 20#'
This is an iPage page software. This aluminum pad has a rather low contact fine-axis property. Figure 8 (b) Fi, two layers of chromium 21 and gold 22 are formed on aluminum laminate.This is called a gold pad.If the surface of the laminate is gold, it has electrical conductivity. The reliability of the one-temperature connection with the photosensitive material having 0 is very high.
It goes without saying that the chip may be one with a /( pump 23 as shown in FIG. 8(c)).
銅９図は、本発明において用いるＩＣチップの常ＩＣチ
ップの側Ｉ］ｉｌｉはシリコンが露出しているために、
ボンディングの際にシ曹−トを起こす可能性が大きい。Figure 9 shows the normal IC chip side I]ili of the IC chip used in the present invention because silicon is exposed.
There is a high possibility that carbonate will occur during bonding.
したがって図の如く、シリコン露出面を絶縁物にておお
う必要がある。絶縁物は樹脂でもよいし、オだ８１０２
等の無榛物でもよい。Therefore, as shown in the figure, it is necessary to cover the exposed silicon surface with an insulator. The insulator may be resin, or Oda8102
It may be a plain item such as.
鎮１０図は本発明による他の実施例を示す。図図の２５
はＩＣチップ、２６け電気伝導性を有する感光性材料、
２７け透明基板である。本発明はこの実施例の如く一度
に複数個（７１Ｃチツプを同時経ボンディングすること
が可能である。Figure 10 shows another embodiment according to the invention. Figure 25
is an IC chip, a photosensitive material with 26 electrical conductivity,
27 transparent substrates. According to the present invention, as in this embodiment, a plurality of 71C chips can be bonded simultaneously.
ｗＬ１１図は本発明の他の実施例を示す０図中の（ａ）
Ｆｉ透明基板上の配線パターン図を示す。図中の２８
は透明基板、２９汀金属パターン剖、５０は透明溝１験
、例えば８ｎ０２ 、 Ｉｎ１Ｊの薄Ｗパターンである
。またＡｔｊＩＯチップのボンディング後の位曾を示す
想像線である。金属パターンｓ２９の位１ｉ１は、ＩＣ
チップ上のポンディングパッド（ｌｉ位診と対応してい
る。このような透明基板を用いて、＃５図にてｉ［＃し
た製造プロナスにてボンティングした後の図を第１１図
（ｂ）Ｋ示す０図中の６１は電気伝導性を有する感光性
材料、３２け工Ｃチップである。本実施例においては、
感光性材料はＩＣのポンディングパッド上にのみ存在す
るためＩＣチップの側面のシリコン露出部にてシ曹−ト
することはない。Figure wL11 is (a) in Figure 0 showing another embodiment of the present invention.
A diagram of the wiring pattern on the Fi transparent substrate is shown. 28 in the diagram
29 is a transparent substrate, 50 is a transparent groove, for example, a thin W pattern of 8n02, In1J. It is also an imaginary line showing the position of the AtjIO chip after bonding. Metal pattern s29 digit 1i1 is IC
The bonding pad on the chip (corresponds to the li position diagnosis). Using such a transparent substrate, the diagram after bonding with the manufacturing pronus shown in Figure #5 is shown in Figure 11 (b). 61 in the figure 0 shown in )K is a 32-wire C chip made of a photosensitive material having electrical conductivity.In this example,
Since the photosensitive material is present only on the IC's bonding pads, it is not deposited on the exposed silicon on the sides of the IC chip.
本発明は以上多くの実施例において説明した如く、透明
基板上ＫＩＯＩＣチップンディングするのに、電気伝導
性を有する感光性材料を用いて電気的に接続することを
＠拳とするＸａの実装方式に関するもの、であり、液晶
パネル、ＢＬパネルあるいけプラズマパネルのドライバ
エＣのチップオンパネル実装方式として大変有望である
。As explained in the many embodiments above, the present invention relates to an Xa mounting method that uses a photosensitive material having electrical conductivity to electrically connect KIOIC chips on a transparent substrate. It is very promising as a chip-on-panel mounting method for driver panels such as liquid crystal panels, BL panels, and plasma panels.
第１図〜８１１２図は、フリップチップの７工イスダウ
ンボンデイング方式の説明図。第５図〜ｌｌＫ１１図は
本発明による工０チップのボンディング方式を鰭明する
図。
１・・・・・・基板
２・・・・・・配線
３・・・・・・ＩＣチップ
４・・・・・・ポンディングパッド
５・−・・■ハンダ
６・・・・・・ハンダバンプ
７・・・・・・透明基板
８・・・・・・配線
９・・・・・・ＩＣチップ
１０・・・・・・ポンディングパッド
１１・・・・・・電気伝導性を有する感光性材料１２・
・・・・・配線（金Ｍ）
１３・・・・・・電気伝導性を有する感光性材料１４・
・・・・・ＩＣチップ
１５・・・・・・光
１６・・・・・・硬化した感光性材料
１７・・・・・・シリコン基板
１８・・・・・・絶縁層
１９・−・・・・アルミニウム層
２０・・・・・・パッジベージ、ン層
２１・・・・・・クロム層
２２・・・・・・金層
２３・・・・・・バンプ
２４・・・・・・絶縁物
２５・・・・・・工０チップ
２６・・・・・・電気伝導性を有する感光性材料２７・
・・・・・透明基板
２８・・・・・・透明基板
２９・・・・・・金属パターン
３０・・・・・・ネサパターン
３１・・・・・・電気伝導性を有する感光性材料３２・
・・・・・ＩＣチップ
以 上
出願人 株式会社 諏訪精工前
代理人 弁理士 最上 務
１１１：
第１図
第２′ＩＬ
第３図
第４図
（（１１
第５図
第６図
第７図
ｅｌ
第８図
第１０図
（η２
Ｇ）
第１１図1 to 8112 are explanatory diagrams of a flip chip 7-chair down bonding method. FIGS. 5 to 11K are diagrams illustrating the bonding method for zero chips according to the present invention. 1... Board 2... Wiring 3... IC chip 4... Ponding pad 5... ■ Solder 6... Solder bump 7...Transparent substrate 8...Wiring 9...IC chip 10...Ponding pad 11...Photosensitive with electrical conductivity Material 12・
... Wiring (gold M) 13 ... Photosensitive material with electrical conductivity 14.
...IC chip 15 ... Light 16 ... Cured photosensitive material 17 ... Silicon substrate 18 ... Insulating layer 19 ... ... Aluminum layer 20 ... Pudge page, n layer 21 ... Chrome layer 22 ... Gold layer 23 ... Bump 24 ... Insulator 25... Process 0 chip 26... Photosensitive material with electrical conductivity 27.
...Transparent substrate 28...Transparent substrate 29...Metal pattern 30...Nesa pattern 31...Photosensitive material 32 with electrical conductivity
...IC chips and above Applicant Suwa Seiko Co., Ltd. Former agent Patent attorney Tsutomu Mogami 111: Figure 1 Figure 2'IL Figure 3 Figure 4 ((11 Figure 5 Figure 6 Figure 7 EL) Figure 8 Figure 10 (η2 G) Figure 11
Claims (6)
明基板上にメンディングした半導体集積回路装置におい
て、皺半導体集積回路チップのポンディングパッドと核
透明基板上の配線とは、電気伝導性を有する感光性材料
にて接続されていることを特徴とする半導体集積回路装
置。(1) In a semiconductor integrated circuit device in which one or more semiconductor integrated circuit chips are mended on a transparent substrate, the bonding pads of the wrinkled semiconductor integrated circuit chips and the wiring on the core transparent substrate are electrically conductive. 1. A semiconductor integrated circuit device connected by a photosensitive material having:
機樹脂を含む感光性有機樹脂であることを特徴とする特
許請求の範囲第１項記載の半導体集積回路！！鎗。(2) The semiconductor integrated circuit according to claim 1, wherein the photosensitive material having electrical conductivity is a photosensitive organic resin containing a conductive organic resin! ! Spear.
いけ炭素の微粉末粒子を含む感光性有機樹脂であること
を特徴とする特許請求の範囲第１項記載の半導体集積回
路装置。(3) The semiconductor integrated circuit device according to claim 1, wherein the photosensitive material having electrical conductivity is a photosensitive organic resin containing fine powder particles of metal or carbon.
が被すされた透明溝Ｗ＃であることを特徴とする特Ｖ！
Ｆ請求の範囲第１項記載の半導体集積回路装置。(4) Special V! feature that the arrangement If1#″t on the transparent substrate is a transparent groove W# partially covered with the gold N pancreas!
F. A semiconductor integrated circuit device according to claim 1.
は、最上金属層が金であることを特徴とする特許請求の
範囲部ＩＸＪ！ｅ載の半導体集積回路装置。(5) Claim IXJ!, wherein the uppermost metal layer of the bonding pad of the semiconductor integrated circuit chip is gold. e-mounted semiconductor integrated circuit device.
の一枚であることを特徴とする特許請求の範囲第１項記
載の半導体集積回路装置。(6) The semiconductor integrated circuit device according to claim 1, wherein the transparent substrate is one of the transparent substrates constituting a liquid crystal display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15117181A JPH0230579B2 (en) | 1981-09-24 | 1981-09-24 | HANDOTAISHUSEKIKAIROSOCHI |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15117181A JPH0230579B2 (en) | 1981-09-24 | 1981-09-24 | HANDOTAISHUSEKIKAIROSOCHI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5852864A true JPS5852864A (en) | 1983-03-29 |
| JPH0230579B2 JPH0230579B2 (en) | 1990-07-06 |
Family
ID=15512860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15117181A Expired - Lifetime JPH0230579B2 (en) | 1981-09-24 | 1981-09-24 | HANDOTAISHUSEKIKAIROSOCHI |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0230579B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6170963U (en) * | 1984-10-15 | 1986-05-15 | ||
| JPH01257407A (en) * | 1988-04-08 | 1989-10-13 | Ishikawajima Shibaura Kikai Kk | Fertilizer application and device therefor |
| US5352318A (en) * | 1989-08-17 | 1994-10-04 | Canon Kabushiki Kaisha | Method of mutually connecting electrode terminals |
| EP0896427A2 (en) * | 1997-08-05 | 1999-02-10 | Nec Corporation | Surface acoustic wave device |
| KR100339016B1 (en) * | 1998-10-02 | 2002-10-25 | 한국과학기술원 | multi-chip package of millimeter wave band using quartz base |
-
1981
- 1981-09-24 JP JP15117181A patent/JPH0230579B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6170963U (en) * | 1984-10-15 | 1986-05-15 | ||
| JPH0412705Y2 (en) * | 1984-10-15 | 1992-03-26 | ||
| JPH01257407A (en) * | 1988-04-08 | 1989-10-13 | Ishikawajima Shibaura Kikai Kk | Fertilizer application and device therefor |
| US5352318A (en) * | 1989-08-17 | 1994-10-04 | Canon Kabushiki Kaisha | Method of mutually connecting electrode terminals |
| EP0896427A2 (en) * | 1997-08-05 | 1999-02-10 | Nec Corporation | Surface acoustic wave device |
| EP0896427A3 (en) * | 1997-08-05 | 2001-01-10 | Nec Corporation | Surface acoustic wave device |
| KR100339016B1 (en) * | 1998-10-02 | 2002-10-25 | 한국과학기술원 | multi-chip package of millimeter wave band using quartz base |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0230579B2 (en) | 1990-07-06 |
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