JPS5851544A - 半導体装置のパツケ−ジ - Google Patents

半導体装置のパツケ−ジ

Info

Publication number
JPS5851544A
JPS5851544A JP15016781A JP15016781A JPS5851544A JP S5851544 A JPS5851544 A JP S5851544A JP 15016781 A JP15016781 A JP 15016781A JP 15016781 A JP15016781 A JP 15016781A JP S5851544 A JPS5851544 A JP S5851544A
Authority
JP
Japan
Prior art keywords
package
conductor layer
semiconductor device
plating
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15016781A
Other languages
English (en)
Japanese (ja)
Other versions
JPS634710B2 (enrdf_load_stackoverflow
Inventor
Noriaki Shiba
柴　典章
Eiji Aoki
英二 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15016781A priority Critical patent/JPS5851544A/ja
Publication of JPS5851544A publication Critical patent/JPS5851544A/ja
Publication of JPS634710B2 publication Critical patent/JPS634710B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP15016781A 1981-09-22 1981-09-22 半導体装置のパツケ−ジ Granted JPS5851544A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15016781A JPS5851544A (ja) 1981-09-22 1981-09-22 半導体装置のパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15016781A JPS5851544A (ja) 1981-09-22 1981-09-22 半導体装置のパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS5851544A true JPS5851544A (ja) 1983-03-26
JPS634710B2 JPS634710B2 (enrdf_load_stackoverflow) 1988-01-30

Family

ID=15490963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15016781A Granted JPS5851544A (ja) 1981-09-22 1981-09-22 半導体装置のパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS5851544A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112921A (ja) * 1984-06-26 1986-01-21 Toyobo Co Ltd 合成繊維のハツ水加工法
JPS6177345A (ja) * 1984-09-21 1986-04-19 Fujitsu Ltd 半導体装置の製造方法
JPS62214648A (ja) * 1986-03-15 1987-09-21 Ngk Insulators Ltd 半導体素子用パツケ−ジの製造方法
US5507989A (en) * 1992-04-01 1996-04-16 Teijin Limited High speed process for producing polyester filaments

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112921A (ja) * 1984-06-26 1986-01-21 Toyobo Co Ltd 合成繊維のハツ水加工法
JPS6177345A (ja) * 1984-09-21 1986-04-19 Fujitsu Ltd 半導体装置の製造方法
JPS62214648A (ja) * 1986-03-15 1987-09-21 Ngk Insulators Ltd 半導体素子用パツケ−ジの製造方法
US5507989A (en) * 1992-04-01 1996-04-16 Teijin Limited High speed process for producing polyester filaments
US5607634A (en) * 1992-04-01 1997-03-04 Teijin Limited High speed process for producing polyester filaments

Also Published As

Publication number Publication date
JPS634710B2 (enrdf_load_stackoverflow) 1988-01-30

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