JPS584978A - Lateral junction type field-effect transistor - Google Patents

Abstract

PURPOSE:To decrease gate leakage by shortening a distance alpha between a source and an upper gate to a distance necessary for obtaining breakdown voltage (BVSGO) between the source and the gate required and sufficiently widening a distance beta between a drain and the upper gate. CONSTITUTION:In the J-FET, the distance beta between the drain 8 and the upper gate 4 is set to value longer than the distance alpha between the source 5 and the gate 4. Accordingly, the interchangeability of the source and the drain is lost and the BVSGO is increased to obtain only value required, but a depletion layer is widely extended to the drain side because the distance beta is, on the other hand, selected at sufficiently large value. When a surface protective film is reinforced or a field plate electrode is attached onto the exposed end of a P-N junction 11 between an epitaxial layer 2 and the upper gate layer 4 through an insulating film, the depletion layer in the vicinity of the surface further increases the effect of its extension. When the depletion layer is widened, field focussing is weakened, excessive gate leakage currents are decreased and high-dielectric resistance operation is enabled.

Description

Detailed Description of the Invention This invention relates to a lateral junction field effect transistor (hereinafter referred to as J-
F]IfT$).

FIG. 1 shows the general structure of a conventional J-PET of this type.

In the figure, (1) is one conductivity type (
For example, P type) semiconductor substrate, (the smell is this semiconductor substrate (1
) is formed on a semiconductor layer (3) of a relatively low impurity concentration and of an opposite conductivity type (for example, N type), and is provided so as to reach the semiconductor substrate (1) K from the surface of this semiconductor layer (2). , an isolation region of one conductivity type surrounding a predetermined region of the semiconductor layer (2), and (4) a region between the semiconductor substrate (1) and the semiconductor layer (2) surrounded by the isolation region (3). An upper gate region of one conductivity type selectively provided at intervals in the dark, (η and (8)
) are selectively provided in the semiconductor layer (2) surrounded by the isolation region (3), and are of opposite conductivity type and have a higher impurity concentration than the semiconductor layer (2). (5) is the source region consisting of the semiconductor layer (2) near the high concentration source region (η), (6) the high concentration drain region (8) is
The drain region (9) is made up of the semiconductor layer (2) in the vicinity, the channel region (11) is made of the semiconductor layer between the semiconductor substrate (1) and the upper dirt region (4), and (11) is the drain region made of the semiconductor layer (1). and the gate region (4) and the semiconductor layer (2).
) It is a PN junction formed in the dark.

The working principle of mK and Kono J-FliT will be briefly explained.

J-PIIfT, source region (5) and gate region (4)
) and (1) to form a PN junction (11
In J-FIT, which is a voltage-driven active element that operates by changing the conductance of the Janel region (9) by extending the depletion layer from the upper channel region (9) to the channel region (9), the source-gate breakdown voltage ( VaG)
Applying the drain-source voltage Vps while keeping it constant,
When the drain current (more than
), the extension of the depletion layer (lO) is f' as shown in Figure 2.
r channel region (due to the voltage drop F in the source (5) II
The extension at drain (6) III is greater than at I. At this time, drain-gate breakdown voltage (B
Voao), the depletion layer (lO) is located in the heavily doped drain region (
8) and the extension of the depletion layer (10) is suppressed, pre-depletion does not occur until the electric field strength reaches the critical strength of the semiconductor.
The depletion layer 10) had reached the highly doped drain region (8).

In J-PET with a conventional structure, it is convenient to have a symmetrical pattern for the lease region and drain region, but the characteristics do not change even if the source and drain are reversed. The distance ° (hereinafter referred to as β) > Fi was the same. However, when Vns was applied, the drain current (
8) when performing the actual operation.
The leakage current (hereinafter referred to as excess gate leakage current) is
In the case of N-channel J-IFIIIT, although there are some differences depending on the model, the voltage increases rapidly from around 15V at Vps+-11), and as a result, there is a drawback that high voltage withstand operation is not possible in actual operation of J-PET. . In addition, the source-to-gate breakdown voltage (BYgoo) of J-FICT
l, T-PET +7) In the operating state, the channel region (height a) is several μm, so the channel region (→
Ku number V is sufficient for pinch-off, and BV
A value much smaller than DGO is fine (but it is not necessary to set it to the same value as BVoao.

However, since the cause of excessive dirt leakage current in J-PIIfT was unknown, there was not much merit in making β larger than α, and in fact, it was more advantageous to keep α and β at the same distance. It is considered to be large'fc.

However, recently, the cause of excessive gate leakage current is
It was found that the following is true. N-channel J-I
In the case of FleT, the gate is always at a negative voltage with respect to the source and drain. When Vpa increases in this state, the drain side electric field of the channel region (9) increases, and minority carriers are generated due to a weak avalanche multiplication effect that causes electron impact ionization. It was found that this is because these minority carriers flow into the gate and cause an increase in leakage current. In order to reduce this leakage current, it is necessary to weaken the electric field strength on the drain side.

The present invention was made in view of the above four points, and by reducing α to the distance necessary to obtain the required BVsgo and making β sufficiently wide, the depletion layer on the drain side can be widened, The idea is to weaken the concentration of the electric field and reduce excessive dirt leakage current.

An embodiment of the present invention will be explained below.

As shown in FIG. 3, the device according to the present invention is designed so that β is larger than α. In such a structure, there is no compatibility between the source and the drain, and the structure is such that only the required BVoao value is produced, and no higher breakdown voltage is required. - Since β is set sufficiently large, the depletion layer (10) strengthens the passivation film on the surface of the drain current, or the field plaid electrode is connected to the semiconductor layer (2) and the upper gate region ( If the surface condition is improved by a method such as depositing the PN junction (11) on the exposed part of the PN junction (11) via an insulating film, the depletion layer in the vicinity of the surface will spread more widely and the effect will increase.

The fact that the depletion layer extends widely weakens the electric field concentration, and as a result, excessive gate leakage current decreases, making it possible for the device to operate at a high breakdown voltage.

As mentioned above, Book 11slJノ, y-ymyFi, BY
The purpose is to reduce excessive dirt leakage current by designing optimal α and β for each of the agO and BVDGO values.

This invention can be implemented only by changing the pattern.

Of course, the manufacturing process can be the same as conventional methods.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional J-FIT, FIG. 2 is a sectional view showing the extension of a depletion layer of a conventional J-PIBT, and FIG. 3 is a sectional view showing a first embodiment of the present invention. . In the figure, (1) is a semiconductor substrate, (2) is a semiconductor layer,
(4) is the upper gate region, ('nFi high-concentration source region, and (8) is the high-concentration drain region. The same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - No. Figure 2 Figure 3 345-

Claims (1)

[Claims] A semiconductor substrate of one conductivity type constituting the lower gate region, a semiconductor layer of the opposite conductivity type formed on this semiconductor substrate, and a semiconductor layer selectively provided within this semiconductor layer at a distance from the semiconductor substrate. An upper gate region of one conductivity type, and a highly doped source region and a highly doped drain region of the opposite conductivity type, which are selectively provided in the semiconductor layer at positions on both sides of the upper gate region, and have a higher impurity concentration than the semiconductor layer. A lateral junction field effect transistor, characterized in that the distance between the highly doped drain region and the upper gate region is greater than the distance between the highly doped source region and the upper dirt region.