JPS584978A - Lateral junction type field-effect transistor - Google Patents
Lateral junction type field-effect transistorInfo
- Publication number
- JPS584978A JPS584978A JP10406581A JP10406581A JPS584978A JP S584978 A JPS584978 A JP S584978A JP 10406581 A JP10406581 A JP 10406581A JP 10406581 A JP10406581 A JP 10406581A JP S584978 A JPS584978 A JP S584978A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- distance
- drain
- region
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 201000003373 familial cold autoinflammatory syndrome 3 Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は横形接合形電界効果トランジスタ(以下J−
F]IfT$と称す)の改良に関するものである。Detailed Description of the Invention This invention relates to a lateral junction field effect transistor (hereinafter referred to as J-
F]IfT$).
従来のこの種J−PETの概要構造を第1図に示す。FIG. 1 shows the general structure of a conventional J-PET of this type.
図において、(1)は下部ゲート領域となる一導電形(
例えばP形)の半導体基板、(匂はこの半導体基板(1
)上に形成された比較的低不純物濃度で反対導電形(例
えばN形)の半導体層、(3)はこの半導体層(2)の
表面から上記半導体基板(1)K達するように設けられ
て、上記半導体層(2)の所定領域を取り囲む一導電形
の分離領域、(4)はこの分離領域(3)で取り囲まれ
た上記半導体層(2)内に、上記半導体基板(1)との
闇に間隔をおいて選択的に設けられた一導電形の上部ゲ
ート領域、(ηおよび(8)はこの上部ゲート領域(4
)の両側の位置で、上記分離領域(3)で取り囲まれた
上記半導体層(2)内にそれぞれ選択的に設けられ、上
記半導体層(2)より不純物濃度が高い反対導電形の高
濃度ソース領域および高濃度ドレイン領域、(5)は上
記高濃度ソース領域(η近傍の半導体層(2)からなる
ソース領域、(6)Fi上記高濃度ドレイン領域(8)
近傍の半導体層(2)からなるドレイン領域、(9)は
上記半導体基板(1)と上部ダート領域(4)間の半導
体層(匂からなるチャネール領域、(11)は上記半導
体基板(1)及び上記ゲート領域(4)と半導体層(2
)闇に形成されるPN接合である。In the figure, (1) is one conductivity type (
For example, P type) semiconductor substrate, (the smell is this semiconductor substrate (1
) is formed on a semiconductor layer (3) of a relatively low impurity concentration and of an opposite conductivity type (for example, N type), and is provided so as to reach the semiconductor substrate (1) K from the surface of this semiconductor layer (2). , an isolation region of one conductivity type surrounding a predetermined region of the semiconductor layer (2), and (4) a region between the semiconductor substrate (1) and the semiconductor layer (2) surrounded by the isolation region (3). An upper gate region of one conductivity type selectively provided at intervals in the dark, (η and (8)
) are selectively provided in the semiconductor layer (2) surrounded by the isolation region (3), and are of opposite conductivity type and have a higher impurity concentration than the semiconductor layer (2). (5) is the source region consisting of the semiconductor layer (2) near the high concentration source region (η), (6) the high concentration drain region (8) is
The drain region (9) is made up of the semiconductor layer (2) in the vicinity, the channel region (11) is made of the semiconductor layer between the semiconductor substrate (1) and the upper dirt region (4), and (11) is the drain region made of the semiconductor layer (1). and the gate region (4) and the semiconductor layer (2).
) It is a PN junction formed in the dark.
mK、コノJ−FliTの1作原理を簡単に説明する。The working principle of mK and Kono J-FliT will be briefly explained.
J−PIIfTけ、ソース領域(5)とゲート領域(4
)及び(1)間に逆バイアスを印加し、PN接合(11
)からの空乏層上チャネル領域(9)に延ばす事により
、町ヤネル領域(9)のコンダクタンスを変化させて動
作する電圧駆動形の能動素子である、
J−FITにおいて、ソース・ゲート間耐圧(VaG)
を一定にしてドレイン・ソース間電圧Vpsを印加し、
ドレイン電流(よりりを流した場合、チャネル領域(9
)の空乏層(lO)の延びは、第2図に示す如く、f’
rネル領域(呻での電圧降Fの為に、ソース(5)II
Iよりドレイン(6)IIIでの延びの方が大きくなる
。この時、ドレイン・ゲート間プレイクダクン耐圧(B
Voao)は、空乏層(lO)が高濃度ドレイン領域(
8)に到達して空乏層(10)の延びがおさえられても
、電界強度が半導体の臨界強度に到するまではプレイク
ダクンを起こさないので、通常はグレイクダクン以In
JK”l!空乏層10)が高濃度ドレイン領域(8)に
到達していた。J-PIIfT, source region (5) and gate region (4)
) and (1) to form a PN junction (11
In J-FIT, which is a voltage-driven active element that operates by changing the conductance of the Janel region (9) by extending the depletion layer from the upper channel region (9) to the channel region (9), the source-gate breakdown voltage ( VaG)
Applying the drain-source voltage Vps while keeping it constant,
When the drain current (more than
), the extension of the depletion layer (lO) is f' as shown in Figure 2.
r channel region (due to the voltage drop F in the source (5) II
The extension at drain (6) III is greater than at I. At this time, drain-gate breakdown voltage (B
Voao), the depletion layer (lO) is located in the heavily doped drain region (
8) and the extension of the depletion layer (10) is suppressed, pre-depletion does not occur until the electric field strength reaches the critical strength of the semiconductor.
The depletion layer 10) had reached the highly doped drain region (8).
従来の構造のJ−PETにおいては、リース領域とドレ
イン領域を対称パターンにした万がソースとドレインを
逆にしても特性が変らないので便利でン領域(8)と上
部ゲート領域(4)間距離°(以下βとする>Fi同じ
であった。ところが、Vnsを印加しド・レイン電流(
より8)を流して実際の動作を行っている時のゲート・
リーク電流(以下過剰ゲート・リーク電流と称す)が、
N−チャネルJ−IFIIITの場合、機種によって多
少の違いはあるが、Vps+−11)=15V位から急
激に増加し、その結果J−PETの実動作においては高
耐圧動作が出来ない欠点がある。又、J−FICTのソ
ース・ゲート間グレイクダクン耐圧(BYgoo)jd
l、T−PET +7)動作状態においてはチャネル領
域(鴫の高さくa)が数μmなので、チャネル領域(→
がピンチオフするためKu数Vあれば十分であり、BV
DGOよりかなり小さな値で良(、BVoaoと同じ値
にする必*Fiない。In J-PET with a conventional structure, it is convenient to have a symmetrical pattern for the lease region and drain region, but the characteristics do not change even if the source and drain are reversed. The distance ° (hereinafter referred to as β) > Fi was the same. However, when Vns was applied, the drain current (
8) when performing the actual operation.
The leakage current (hereinafter referred to as excess gate leakage current) is
In the case of N-channel J-IFIIIT, although there are some differences depending on the model, the voltage increases rapidly from around 15V at Vps+-11), and as a result, there is a drawback that high voltage withstand operation is not possible in actual operation of J-PET. . In addition, the source-to-gate breakdown voltage (BYgoo) of J-FICT
l, T-PET +7) In the operating state, the channel region (height a) is several μm, so the channel region (→
Ku number V is sufficient for pinch-off, and BV
A value much smaller than DGO is fine (but it is not necessary to set it to the same value as BVoao.
しかし、従来は、J−PIIfTの過剰ダート・リーク
電流の発生原因が不明であった為、βをαより大きくす
るメリットは余りなく、むしろαとβを同じ距離にして
おいた方がメリットが大きいと考えられてい′fc。However, since the cause of excessive dirt leakage current in J-PIIfT was unknown, there was not much merit in making β larger than α, and in fact, it was more advantageous to keep α and β at the same distance. It is considered to be large'fc.
ところが最近、過剰ゲート・リーク電流発生の原因は、
下記の通りであることがわかった。N−チャネルJ−I
FleTの場合、ゲートはソースとドレインに対して常
に負の電圧になっている。このような状態でVpaが増
加すると、チャネル領域(9)のドレイン側電界が高ま
り、電子の衝突電離を起こす弱いなだれ増倍効果によっ
て少数キャリヤーが発生する。この少数キャリヤーがゲ
ートへ流れ込んでリーク電流の増加となる為であること
がわかった。このリーク電流を減少させる為には、ドレ
イン側での電界強度を弱める必要がある。However, recently, the cause of excessive gate leakage current is
It was found that the following is true. N-channel J-I
In the case of FleT, the gate is always at a negative voltage with respect to the source and drain. When Vpa increases in this state, the drain side electric field of the channel region (9) increases, and minority carriers are generated due to a weak avalanche multiplication effect that causes electron impact ionization. It was found that this is because these minority carriers flow into the gate and cause an increase in leakage current. In order to reduce this leakage current, it is necessary to weaken the electric field strength on the drain side.
本発明はこのよう4点に鑑みてなされ六本ので、αを要
求されるBVsgo を得るのに必要な距離に縮メ、か
つβを十分広く取る事により、ドレイン側の空乏層を広
く延ばし、電界の集中を弱めて過剰ダート・リーク電流
を減少させようとするものである。The present invention was made in view of the above four points, and by reducing α to the distance necessary to obtain the required BVsgo and making β sufficiently wide, the depletion layer on the drain side can be widened, The idea is to weaken the concentration of the electric field and reduce excessive dirt leakage current.
以下、本発明の一実施例にりいて説明する。An embodiment of the present invention will be explained below.
第3図に示す如く、本発明による素子は、αよりβの方
が大きくなるように設計されている。このような構造に
おいては、ソースとドレインの互換性はなく、要求され
るBVoao値が出るにとどめ、それ以上の耐圧は出な
くても良い構造となっている。−万、βは十分大きく取
っである為に、空乏層(10)はドレイン電流
表面のパッシベイション膜を強化する、あるい−はフィ
ールドプレイド電極を半導体層(2)と上部ゲート領域
(旬間のPN接合(11)の露出部上に絶縁膜を介して
被着する等の方法で表面状態を良好にすると、表面近傍
の空乏層はさらに広く延で、効果は増大する。As shown in FIG. 3, the device according to the present invention is designed so that β is larger than α. In such a structure, there is no compatibility between the source and the drain, and the structure is such that only the required BVoao value is produced, and no higher breakdown voltage is required. - Since β is set sufficiently large, the depletion layer (10) strengthens the passivation film on the surface of the drain current, or the field plaid electrode is connected to the semiconductor layer (2) and the upper gate region ( If the surface condition is improved by a method such as depositing the PN junction (11) on the exposed part of the PN junction (11) via an insulating film, the depletion layer in the vicinity of the surface will spread more widely and the effect will increase.
空乏層が広く延びるという事は電界集中を弱めるという
事であり、その結果、過剰ゲート・リーク電流は減少し
、素子の高耐圧動作が可能となる。The fact that the depletion layer extends widely weakens the electric field concentration, and as a result, excessive gate leakage current decreases, making it possible for the device to operate at a high breakdown voltage.
上述ノ如< 、本11slJノ、y−ymyFi、BY
agO、BVDGO値それぞれに対して最適のα、βを
設計する事により、過剰ダート・リーク電流を減少させ
ようとするものである。As mentioned above, Book 11slJノ, y-ymyFi, BY
The purpose is to reduce excessive dirt leakage current by designing optimal α and β for each of the agO and BVDGO values.
本・発明はパターン変更のみで実施可能であり。This invention can be implemented only by changing the pattern.
製造プロセス等は従来と同じ方法で製造することが出来
るのけもちろんである。Of course, the manufacturing process can be the same as conventional methods.
第1図は従来のJ−FITを示す断面図、第2図は従来
のJ−PIBTの空乏層の延びを示す断面図、第3図は
本発明の′一実施例を示す断面図である。
図において、(1)は半導体基板、(2)は半導体層、
(4)は上部ゲート領域、(′nFi高濃度ソース領域
、(8)は高濃度ドレイン領域である。
なお、図中同一符号は同−又は相当部分を示す。
代 理 人 葛 野 信 −第2図
第3図
345−FIG. 1 is a sectional view showing a conventional J-FIT, FIG. 2 is a sectional view showing the extension of a depletion layer of a conventional J-PIBT, and FIG. 3 is a sectional view showing a first embodiment of the present invention. . In the figure, (1) is a semiconductor substrate, (2) is a semiconductor layer,
(4) is the upper gate region, ('nFi high-concentration source region, and (8) is the high-concentration drain region. The same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - No. Figure 2 Figure 3 345-
Claims (1)
半導体基板上に形成された反対導電形の半導体層、この
半導体層内に上記半導体基板との闇に間隔をおいて選択
的に設けられた一導電形の上部ゲート領域、この上部ゲ
ート領域の両側の位置でそれぞれ上記半導体層内に選択
的に設けられ、上記半導体層より不純物濃度が高い反対
導電形の高濃度ソース領域と高濃度ドレイン領域を備え
、上記高濃度ドレイン領域と上部ゲート領域間の距離を
上記高濃度ソース領域と上部ダート領域間の距離より大
きくしたことを特徴とする横形接合形電界効果トランジ
スタ。A semiconductor substrate of one conductivity type constituting the lower gate region, a semiconductor layer of the opposite conductivity type formed on this semiconductor substrate, and a semiconductor layer selectively provided within this semiconductor layer at a distance from the semiconductor substrate. An upper gate region of one conductivity type, and a highly doped source region and a highly doped drain region of the opposite conductivity type, which are selectively provided in the semiconductor layer at positions on both sides of the upper gate region, and have a higher impurity concentration than the semiconductor layer. A lateral junction field effect transistor, characterized in that the distance between the highly doped drain region and the upper gate region is greater than the distance between the highly doped source region and the upper dirt region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10406581A JPS584978A (en) | 1981-07-01 | 1981-07-01 | Lateral junction type field-effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10406581A JPS584978A (en) | 1981-07-01 | 1981-07-01 | Lateral junction type field-effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS584978A true JPS584978A (en) | 1983-01-12 |
Family
ID=14370763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10406581A Pending JPS584978A (en) | 1981-07-01 | 1981-07-01 | Lateral junction type field-effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS584978A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0268136A2 (en) * | 1986-11-18 | 1988-05-25 | TELEFUNKEN electronic GmbH | Semiconductor arrangement |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5367371A (en) * | 1976-11-29 | 1978-06-15 | Sony Corp | Semiconductor device |
JPS548476A (en) * | 1977-06-22 | 1979-01-22 | Seiko Instr & Electronics Ltd | Semiconductor device |
JPS554912A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Fieldeffect lateral transistor |
-
1981
- 1981-07-01 JP JP10406581A patent/JPS584978A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5367371A (en) * | 1976-11-29 | 1978-06-15 | Sony Corp | Semiconductor device |
JPS548476A (en) * | 1977-06-22 | 1979-01-22 | Seiko Instr & Electronics Ltd | Semiconductor device |
JPS554912A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Fieldeffect lateral transistor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0268136A2 (en) * | 1986-11-18 | 1988-05-25 | TELEFUNKEN electronic GmbH | Semiconductor arrangement |
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