JPH01140772A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To allow excessive carriers to be discharged and to improve breakdown voltages by providing in a substrate a region where conductivity is high, and reducing generation of excessive carriers within the substrate and a resistance against an accumulation region. CONSTITUTION:An N-channel MIS transistor comprising a source 1, a drain 2, and a gate 3 is arranged on a P-type silicon substrate, wherein a P<+>-layer 16 which is heavily doped compared to a substrate introduced through a groove- shaped vertical hole is formed, the groove having a highly conductive electrode material 17 buried therein which is in contact with the P<+>-layer 16. According to the constitution, the distance between the accumulation region 8, and the buried region 17 which will be a substrate contact can be short and a resistance therebetween can drastically be reduced by the heavy doping of the P<+>-layer, whereby a source-drain breakdown voltage against avalanche breakdown can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a structure suitable for increasing the withstand voltage of an element and a method for manufacturing the same.

[Conventional technology]

Conventional devices, as discussed in U.S. Pat. No. 4,132,997, use
Contact with the substrate is established on the surface near the MIS type semiconductor device, and excess carriers generated within the substrate are flowed out to improve breakdown voltage.

[Problem that the invention seeks to solve]

Since the above conventional technology causes excess carrier to flow out from one surface, it does not deal with the flow of carrier accumulated deep inside the substrate, and if a large amount of excess carrier is generated, it is not possible to flow out sufficiently, and withstand voltage There were limits to improvement.

An object of the present invention is to facilitate the outflow of excess carriers and improve the breakdown voltage of the transistor.

[Means for solving problems]

The above objective is to easily drain excess carriers and improve breakdown voltage by setting a highly conductive region in the substrate and lowering the resistance with the generation and accumulation region of excess carriers inside the substrate.

[Effect]

FIG. 1 shows the structure of a semiconductor device of the present invention.

The MIS type field effect transistor has a source 1. It consists of a drain 2 and a gate 3. Source 1. When a voltage is applied across the drain 2, electrons or holes, which are carriers, are accelerated by the electric field, impact ionization occurs near the drain 4, and pairs of holes and electrons are generated. FIG. 2 shows impact ionization and subsequent carrier behavior using an n-channel MIS transistor as an example. Electrons accelerated by the source-drain electric field flow along a current path 9 near the surface, undergo in-vacuum ionization in a region 10 near the drain, and generate pairs of electrons and holes. The generated electrons flow through path 11 to the drain, while holes flow through path 12 to the substrate contact. Since the substrate has a resistive component, the potential of the region 13 under the channel increases due to this hole current until it satisfies the forward bias condition of the PN junction between the source and the substrate. Since the potential of region 13 is fixed at a forward bias of about 0.7V, an additional electron current 9 flows between the source and drain, further causing impact ionization, and this positive feedback loop causes a large amount of current to flow between the source and drain. This will cause the so-called avalanche yield phenomenon. The problem here is that the potential is fixed in order to maintain the forward bias, and the holes accumulated in the region 13.

The hole current 15 is determined by the potential difference between the substrate contact and the resistor 14. That is, if the resistance is high, fewer holes will be released in a certain period of time, and if the resistance is low, more holes will be released.

Therefore, by reducing this resistance, the potential rise in the region 13 can be suppressed to below the forward bias, and avalanche breakdown can be prevented unless the number of electron-hole pairs due to impact ionization increases. In other words, the potential difference between the source and drain at which avalanche breakdown occurs can be made larger, and the breakdown voltage of the transistor is improved.

This substrate resistance 14 corresponds to the resistance value between the substrate contact 7 and the storage region 8, as shown in FIG.

As shown in Figure 3, this accumulation region peaks at about 5 μm from the surface, and as is clear from the simulation results,
It was newly discovered that it extends to about 30 μm.

Therefore, source 1. By providing a low resistance region 5 connected to the substrate contact 7 on the side of the drain 2 and existing deep into the substrate as shown in FIG. 3, the effective resistance of the substrate contact 7 and the storage region 8 can be lowered. Although it is possible to form the low resistance region 5 from the surface by ion implantation to improve the breakdown voltage, since the accumulation region 8 exists from about 2 μm to several tens of μm, it is necessary to form it deep. Therefore, a deeper low-resistance region can be formed by once making a hole in the Si substrate and filling the inside with St having a high concentration of impurity. Furthermore, if a conductor such as polycrystalline silicon or metal is buried in this region, the resistance value can be lowered further, or by forming a highly concentrated impurity layer deep into the substrate by ion implantation with a hole formed. A deep low resistance region is obtained,
Improved pressure resistance can be achieved.

The low-resistance region described above is most effective when it is present in both the source and drain regions, but it can function satisfactorily even if it is present in only one region. In this case, since the source potential is lower than that of the drain, it is more advantageous for hole outflow to set it on the source side than on the drain side.

〔Example〕

FIG. 4(a) shows the structure of a semiconductor device according to an embodiment of the present invention. A source 1 and a drain 2 are placed on a P-type Si substrate 6.
．． Gate 3 forms an N-channel MIS transistor. sauce.

A P intermediate layer 1 with a higher concentration than the substrate was introduced through a vertical hole formed in a groove shape with a depth of about 10 μm on the side of the drain.
A highly conductive electrode material 17 is embedded in the groove and is in contact with the P+ layer 16. According to this embodiment, the storage region 8 and the buried region 1 serving as the substrate contact
7 is short and the concentration of the P+ layer is high, the resistance value between the two can be significantly reduced, and the holes accumulated in the substrate can easily flow from the substrate to the substrate contact, reducing the withstand voltage of the source and drain due to avalanche breakdown. As shown in FIG. 4(b), it was possible to improve the voltage by about 1 to 3V.

FIG. 5 shows the structure of a semiconductor device according to an embodiment of the present invention. This is source 1. 5i18 having a high concentration of P-type impurities is embedded in a groove-shaped hole of about 20 μm on the side of the drain 2. This also made it possible to significantly facilitate the release of holes accumulated in the substrate and to improve the source/drain breakdown voltage by about 1 to 3 V.

〔Effect of the invention〕

According to the present invention, since excess electron/hole pairs can be emitted in a short time by impact ionization between the source and drain, avalanche breakdown caused by the positive feedback phenomenon of excess carriers can be controlled, and MIS This has the effect of improving the source-drain breakdown voltage of a type field effect transistor by about 1 to 3 cm.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of the MIS type transistor of the present invention,
FIG. 2 is a diagram explaining the physical phenomenon that is the logical basis of the present invention, FIG. 3 is a diagram showing the depth of the storage region, and FIG. 4 is a cross-sectional view of an MIS field effect transistor according to an embodiment of the present invention. , FIG. 5 shows a sectional view of an MIS type field effect transistor according to an embodiment of the present invention. 1...source, 2...drain, 3...gate. ￥A 1 (2) 42 田ttJlcTgelN C#cl! N7! QnDN I
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Claims (1)

[Claims] 1. In a MIS field effect transistor formed on a semiconductor substrate of a first conductivity type, at least one highly doped semiconductor region is provided outside the semiconductor region of the second conductivity type that forms the source and drain of the MIS field effect transistor. The first plate is large and is formed deep inside the substrate.
A semiconductor device characterized by having a conductive type semiconductor region. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the depth of the highly concentrated semiconductor region of the first conductivity type is at least 2 micrometers or more from the surface of the substrate. 3. In the semiconductor device according to claim 1,
1. A semiconductor device characterized in that a conductive material region is formed in place of a first conductivity type semiconductor region formed deeply and highly concentrated. 4. In a MIS field effect transistor formed on a semiconductor substrate of a first conductivity type, at least one highly doped semiconductor region is formed outside the semiconductor region of the second conductivity type that forms the source and drain of the transistor and deep into the substrate. first formed
In a method for manufacturing a semiconductor device characterized by having a semiconductor region of a conductive type, the first conductive type semiconductor region and the conductive material region formed at high concentration and depth are trenched in the substrate, and then the region is removed. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device.