JPS5834959A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5834959A JPS5834959A JP56134866A JP13486681A JPS5834959A JP S5834959 A JPS5834959 A JP S5834959A JP 56134866 A JP56134866 A JP 56134866A JP 13486681 A JP13486681 A JP 13486681A JP S5834959 A JPS5834959 A JP S5834959A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type
- field effect
- semiconductor substrate
- defect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000007547 defect Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 3
- 239000001301 oxygen Substances 0.000 claims abstract description 3
- 230000005669 field effect Effects 0.000 claims description 24
- 230000000295 complement effect Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 11
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明紘微細化を可能にする相補型電界効果トランジ
スタを有する半導体装置およびその製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having complementary field effect transistors that enables miniaturization, and a method for manufacturing the same.
相補型電界効果トランジスタデバイスは標準の電界効果
デバイスよシ相当に消費電力が少ない利卓があるため、
最近の高密度集積回路化に伴い、従来の電界効果トラン
ジスタデバイスが相補型電界効果トランジスタに置きか
えられるようになった。しかし、この相補型電界効果ト
ランジスタデバイスはＰ型チャンネル電界効果トランジ
スタとＮ型チャンネル電界効果トランジスタとを同一基
板上に形成するため、一般的に単純なＮ型、あるいＨｐ
型の電界効果トランジスタデバイスと比較してパターン
が大きく、動作速度が遅い。しかし、最近では微細加工
技術の向上に伴い、個々のトランジスタが微細化され、
高速性能が得られるようになった。ところで、第１図に
示す相補型電界効果トランジスタデバイスにおいて、Ｐ
型チャンネル電界効果トランジスタとＮ型チャンネル電
界効果トランジスタとを接近させると、寄生のＰＮＰ型
およびＮＰＮ聾のバイポーラ型トランジスタの電流増幅
率が大きくなシ、ＰＮＰＮ型およびＮＰＮＰ型寄生すイ
リスタの動作が容易となる。すなわち、もし出力端子か
ら正電圧のノイズが入っ九場合、Ｎ型つエール（２）中
の出方端子に１＃続するＰ型拡散層（６）からホールが
注入され、このＮ型つェール（２）中で少数キャリアと
なる。ここで、微細化のために、Ｎ型つェール（２）の
拡散層を浅くすると、少数キャリアはＰ型基板（１）へ
抜ける確率が高くなる。っまシ、寄生ＮＰＮ ） ：７
ンジスタの電流増幅率が高くなる。Ｐ型基板（１）にホ
ールが注入されると、電源電圧Ｖｓｓが印加するＮ型拡
散層（１）よりホールと再結合するために電子が注入さ
れ、Ｐ型基板（１）では少数キャリアとなル、一部の電
子ｌｌ１Ｎ型ウエール（２）に到達する。っまシ、微細
化のために、Ｎ型つェールＣ１）とＰ型電界効果トラン
ジスタを近づけると、寄生ＮＰＮ ） ｊンジスタの実
効ベース幅が狭くなって、Ｎ７ウエールＱ）に電子が逆
注入されやすくなる。もしＮ型つェール（２）に多量の
電子が注入すると、このＮ型つェール（２）のＰ型拡散
層（６）からホールが注入され、一部はＮ型つェールＱ
）を通過し、ＰＩＩ基板（１）に注入され、その結果ま
すますＮ型つエール（２）に電子が注入され、最後には
電源電圧在Ｃと電源電圧ＶＳＳとに定常的な電流が流れ
、いわゆるラッチアップ現象が生ずる。また、もし出力
端子に負の電圧のノイズが加わった場合は最初にＮ型チ
ャンネル電界効果トランジスタの出力端子に接続されて
いるＮ型拡散層（７）から電子が注入され、最後にラッ
チアップが起きる。このラッチアップ現象はウエールを
Ｐ型にしても同様に起きる。なお、第１図において、（
３）ｉｉ分離酸化膜、（４）はゲート酸化膜、５）は多
孔質シリコン、（８）はリンガラス膜、（９）は電極で
ある。Complementary field effect transistor devices have the advantage of consuming considerably less power than standard field effect devices.
With the recent trend toward higher density integration, traditional field effect transistor devices have been replaced by complementary field effect transistors. However, since this complementary field effect transistor device forms a P-type channel field effect transistor and an N-type channel field effect transistor on the same substrate, it is generally a simple N-type or Hp
Compared to conventional field effect transistor devices, the pattern is larger and the operating speed is slower. However, with the recent improvement in microfabrication technology, individual transistors have become smaller and smaller.
High-speed performance is now available. By the way, in the complementary field effect transistor device shown in FIG.
When the type channel field effect transistor and the N type channel field effect transistor are brought close together, the current amplification factor of the parasitic PNP type and NPN type bipolar type transistor becomes large, and the operation of the PNPN type and NPNP type parasitic iris is facilitated. becomes. That is, if positive voltage noise enters from the output terminal, holes will be injected from the P-type diffusion layer (6) connected to the output terminal of the N-type wire (2), and this (2) Become a minority carrier. Here, if the diffusion layer of the N-type thale (2) is made shallow for miniaturization, the probability that minority carriers will escape to the P-type substrate (1) increases. Parasitic NPN): 7
The current amplification factor of the transistor increases. When holes are injected into the P-type substrate (1), electrons are injected from the N-type diffusion layer (1) to which the power supply voltage Vss is applied to recombine with the holes, and the P-type substrate (1) becomes minority carriers. Therefore, some electrons reach the ll1N type well (2). However, when an N-type wale C1) and a P-type field effect transistor are brought close together for miniaturization, the effective base width of the parasitic NPN transistor becomes narrower, and electrons are injected back into the N7 well Q). It becomes easier. If a large amount of electrons are injected into the N-type thale (2), holes will be injected from the P-type diffusion layer (6) of the N-type thale (2), and some of them will be injected into the N-type thale Q.
) and are injected into the PII substrate (1), and as a result, more and more electrons are injected into the N-type tube (2), and finally a steady current flows between the power supply voltage C and the power supply voltage VSS. , a so-called latch-up phenomenon occurs. Also, if negative voltage noise is applied to the output terminal, electrons are first injected from the N-type diffusion layer (7) connected to the output terminal of the N-type channel field effect transistor, and finally latch-up occurs. get up. This latch-up phenomenon similarly occurs even if the wale is made of P type. In addition, in Figure 1, (
3) ii isolation oxide film, (4) a gate oxide film, 5) porous silicon, (8) a phosphorus glass film, and (9) an electrode.
このように、従来の相補型電界効果トランジスタを有す
る半導体装置ではＰ型電界効果トランジスタとＮ型電界
効果トランジスタとが接近することによシ、小さいノイ
ズによってもラッチアップが起こる。したがって、この
ラッチアップを防ぐためにはこのＰ型およびＮ型の電界
効果トランジスタをある程度離しておく必要があシ、微
細化のさまたげとなる欠点があった。As described above, in a conventional semiconductor device having complementary field effect transistors, latch-up occurs due to the proximity of the P-type field effect transistor and the N-type field effect transistor, even due to small noise. Therefore, in order to prevent this latch-up, it is necessary to separate the P-type and N-type field effect transistors to some extent, which has the drawback of hindering miniaturization.
したがって、この発明の目的は微細化が可能であシ、シ
かもラッチアップを有効に抑制することができる半導体
装置およびその製造方法を提供するものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that can be miniaturized and can effectively suppress latch-up, and a method for manufacturing the same.
このような目的を達成するため、この発明は半導体基板
表面からウエール深さ近傍までに形成される無欠陥層お
よびその基板内部に形成した結晶欠陥層からなる半導体
基板上に相補型電界効果トランジスタを形成するもので
あり、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention provides a complementary field effect transistor on a semiconductor substrate consisting of a defect-free layer formed from the surface of the semiconductor substrate to near the depth of the wale and a crystal defect layer formed inside the substrate. This will be described in detail below using examples.
第２図はこの発明に係る半導体装置およびその製造方法
の一実施例を示す断面図である。同図において、（１０
）は表面からウエールｆＲキ近傍まで形成され九無欠陥
層（１０ｍ）および内部に形成された結晶欠陥層（１０
ｂ）とを備えたＰ型基板である。FIG. 2 is a sectional view showing an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention. In the same figure, (10
) is formed from the surface to the vicinity of the wale fR and has a nine defect-free layer (10 m) and a crystal defect layer (10 m) formed inside.
b) It is a P-type substrate.
次に、上記構成による半導体装置のラッチアップが有効
に抑制される動作について説明する。例えば出力端子に
正電圧のノイズが入った場合、Ｎ型つエール（２）中の
出力端子に接続されているＰ型拡散層（６）からホール
が注入され、一部はＰ型基板（１０）に注入されるが、
このＰ型基板（１０）の結晶欠陥層（１１１１１ｂ）に
より再結合され、ラッチアップが起こｂにくくなる。例
えばＰ型基板（１０）にホールが残って、Ｎ型チャンネ
ル電界効果トランジスタのＮ型拡散層（７）から電子が
注入されても、電子が結晶欠陥層（１０ｂ）で再結合さ
れ、ラッチアップを防ぐことができる。また、例えば出
力端子に負電圧のノイズが入った場合も同様に、Ｎ型電
界効果トランジスタの出力端子に接続されているＮ型拡
散層（７）から注入された電子は結晶欠陥層（ｔａｂ）
で結合され、Ｎ型つエール（２）から逆注入されるホー
ルも再結合されてラッチアップが防止される。また、能
動領域は無欠陥層（１軛）に形成されているため、易動
度の低下、リーク電流の増大はないことはもちろんであ
る。Next, a description will be given of an operation in which latch-up of the semiconductor device with the above configuration is effectively suppressed. For example, when positive voltage noise enters the output terminal, holes are injected from the P-type diffusion layer (6) connected to the output terminal in the N-type substrate (2), and some of them are ), but
They are recombined by the crystal defect layer (11111b) of this P-type substrate (10), making it difficult for latch-up to occur. For example, even if holes remain in the P-type substrate (10) and electrons are injected from the N-type diffusion layer (7) of the N-type channel field effect transistor, the electrons are recombined in the crystal defect layer (10b) and latch up. can be prevented. Similarly, when negative voltage noise enters the output terminal, for example, electrons injected from the N-type diffusion layer (7) connected to the output terminal of the N-type field effect transistor are transferred to the crystal defect layer (Tab).
The holes injected back from the N-type tube (2) are also recombined to prevent latch-up. Furthermore, since the active region is formed in a defect-free layer (one yoke), there is of course no decrease in mobility and no increase in leakage current.
次に、前記Ｐ型基板（１０）の製造方法について第３図
（＆）および第３図（ｂ）を参照して説明する。まず、
ＣＺ基板を適当な低温熱処理を行なうと、第３図（ａ）
に点（１１）で示すように、結晶欠陥の核を含んだ基板
（１２）が得られる。この基板（１２）を高温で熱処理
を行なうと、基板（１２）の表面近くでは酸素が外方拡
散して核がつぶれ無欠陥層（ｌｅａ）が得られる。Next, a method for manufacturing the P-type substrate (10) will be explained with reference to FIGS. 3(&) and 3(b). first,
When the CZ substrate is subjected to appropriate low-temperature heat treatment, the result is shown in Figure 3 (a).
As shown by point (11), a substrate (12) containing crystal defect nuclei is obtained. When this substrate (12) is heat-treated at a high temperature, oxygen diffuses outward near the surface of the substrate (12), crushing the nuclei, and obtaining a defect-free layer (lea).
一方、この基板（１２）の内部では核が成長し、第３図
伽）に示すように、結晶欠陥層（１−）が形成される。On the other hand, nuclei grow inside this substrate (12), and a crystal defect layer (1-) is formed as shown in FIG. 3).
表お、上記無欠陥層（１０ｍ）の幅は熱処理方法によっ
て制御することができ、通常は第２図に示したように、
Ｎ型つエールＱ）の拡散層の深さと同じ程度に形成され
る。In addition, the width of the defect-free layer (10 m) can be controlled by the heat treatment method, and usually, as shown in Figure 2,
It is formed to the same depth as the diffusion layer of the N-type ale Q).
なお、上記実施例ではＰ型基板を用いてＮ型つエール°
を形成したが、Ｎ−基板を用いてＰ型つエールを形成し
てもよい仁とはもちろんである。まえ、ウェール形成前
での熱処理によって結晶欠陥層を設けているが、ウエー
ル形成後での熱処理によって設けてもよいこと社もちろ
んである。また、熱処理ではなく、イオン注入などのダ
メツジによって結晶欠陥層を形成してもよいことはもち
ろんである。Note that in the above embodiment, a P-type substrate is used and an N-type substrate is used.
However, it is of course possible to form a P-type layer using an N-substrate. Although the crystal defect layer is provided by heat treatment before forming the wale, it is of course possible to provide it by heat treatment after forming the wale. Furthermore, it goes without saying that the crystal defect layer may be formed by damage such as ion implantation instead of heat treatment.
以上詳細に説明したように、この発明に係る半導体装置
によればノイズによってキャリアが異常発生しても、結
晶欠陥層によって再結合させられ、ラッチアップが起き
ない。このため、微細なパターン形成が可能になシ、高
速動作が可能になると共に製造の歩留シが高くなるなど
の効果がある。As described above in detail, according to the semiconductor device according to the present invention, even if carriers are abnormally generated due to noise, they are recombined by the crystal defect layer and latch-up does not occur. Therefore, it is possible to form fine patterns, to operate at high speed, and to increase the manufacturing yield.
第１図は従来の相補型電界効果トランジスタを示す断面
図、第２図はこの発明に係る半導体装置の一実施例を示
す断面図、第３図（１）および第３図伽）は第２図に示
す基板の製造方法の一実施ｆｉｌを示す平面図である。
（１）・・・・Ｐ型基板、ＣＩ）・・・・Ｎ型つエール
、（３）・・・・分離酸化膜、（４）・・・・ゲート酸
化膜、（５）・・・・多孔質シリコン、（６）・・・・
Ｐ型拡散層、σ）・Φ・・Ｎ型拡散層、（８）・・・・
リンガラス層、（ｓ）−−−＠を極、（１０）−−−−
Ｐ型基板、（１０ｍ）・・・・無欠陥層、（１０ｋ）・
・・・結晶欠陥層、（１１）・・・・点、（１２）・−
・一基板。
なお、同一符号は同一または相当部分を示す。
代理人 蔦 野 信 −（外１名）
第１図
第２図
第３図（０）
１
２
第３図（ｂ）FIG. 1 is a sectional view showing a conventional complementary field effect transistor, FIG. 2 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIGS. FIG. 2 is a plan view showing one implementation of the method for manufacturing the substrate shown in the figure. (1)...P-type substrate, CI)...N-type tube, (3)...Isolation oxide film, (4)...Gate oxide film, (5)...・Porous silicon, (6)...
P-type diffusion layer, σ)・Φ...N-type diffusion layer, (8)...
Phosphorous glass layer, (s)---@ pole, (10)----
P-type substrate, (10m)...defect-free layer, (10k)...
...Crystal defect layer, (11) ... point, (12) ...
・One board. Note that the same reference numerals indicate the same or equivalent parts. Agent Shin Tsutano - (1 other person) Figure 1 Figure 2 Figure 3 (0) 1 2 Figure 3 (b)
Claims (2)
された無欠陥層およびその基板内部に形成し九結晶欠陥
層からなる半導体基板上に相補型電界効果トランジスタ
を形成することを特徴とする半導体装置。(1) A complementary field effect transistor is formed on a semiconductor substrate consisting of a defect-free layer formed from the surface of the semiconductor substrate to the vicinity of the wale depth and a nine-crystalline defect layer formed inside the substrate. Semiconductor equipment.
むように形成するｇｉｏ工程と、この第１の工程の後の
半導体基板を高温で熱処理し、半導体基板表面からウエ
ール深さ近傍までは酸素が外方拡散して核がつぶれ無欠
陥層となる第２の工程と、とのｇｚの工程の彼の半導体
基板上に相補型電界効果トランジスタを形成する館３の
工程とからなることを特徴とする半導体装置の製造方法
。(2) A GIO process in which the semiconductor substrate is formed to contain polycrystalline defect nuclei by low-temperature heat treatment, and the semiconductor substrate after this first process is heat-treated at high temperature to extend from the semiconductor substrate surface to the vicinity of the wale depth. consists of a second step in which oxygen diffuses out and the nucleus collapses to form a defect-free layer, and a third step in which a complementary field effect transistor is formed on the semiconductor substrate of the gz step. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134866A JPH0612801B2 (en) | 1981-08-25 | 1981-08-25 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134866A JPH0612801B2 (en) | 1981-08-25 | 1981-08-25 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5834959A true JPS5834959A (en) | 1983-03-01 |
| JPH0612801B2 JPH0612801B2 (en) | 1994-02-16 |
Family
ID=15138299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56134866A Expired - Lifetime JPH0612801B2 (en) | 1981-08-25 | 1981-08-25 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0612801B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143563A (en) * | 1982-02-22 | 1983-08-26 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPS615568A (en) * | 1984-05-22 | 1986-01-11 | Mitsubishi Electric Corp | Manufacture of complementary mos integrated circuit |
| JPS62104486U (en) * | 1985-12-23 | 1987-07-03 | ||
| JPH01161756A (en) * | 1987-11-18 | 1989-06-26 | Intersil Inc | Cmos integrated circuit and its manufacture |
-
1981
- 1981-08-25 JP JP56134866A patent/JPH0612801B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143563A (en) * | 1982-02-22 | 1983-08-26 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH0241175B2 (en) * | 1982-02-22 | 1990-09-14 | Hitachi Ltd | |
| JPS615568A (en) * | 1984-05-22 | 1986-01-11 | Mitsubishi Electric Corp | Manufacture of complementary mos integrated circuit |
| JPH0244152B2 (en) * | 1984-05-22 | 1990-10-02 | Mitsubishi Electric Corp | |
| JPS62104486U (en) * | 1985-12-23 | 1987-07-03 | ||
| JPH0525267Y2 (en) * | 1985-12-23 | 1993-06-25 | ||
| JPH01161756A (en) * | 1987-11-18 | 1989-06-26 | Intersil Inc | Cmos integrated circuit and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0612801B2 (en) | 1994-02-16 |
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