JPH06224209A - Vertical transistor and its manufacture - Google Patents

Abstract

PURPOSE:To suppress the hFE of a parasitic PNP transistor without increasing the size of the vertical NPN transistor. CONSTITUTION:This is equipped with an inner base 8 in low impurity concentration, which is provided on the surface of a single crystal n-type collector layer 3 by introducing boron B, and an outer base 11 in high impurity concentration, which is provided in the region surrounding this inner base 8 by introducing boron B. This is equipped with an emitter region 14, which is provided on the surface of the inner base 8 by introducing n-type impurity elements. A defective layer is provided on the surface of the outer base 11 by implanting inert impurity element ions or ions including inert impurity elements for its composition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical transistor and its manufacturing method, and more particularly to a vertical NPN transistor and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, this type of vertical NPN transistor is manufactured, for example, as follows. First, as shown in FIG. 8A, the N ⁺ type buried layer 102 is provided in a predetermined region on the surface of the P type semiconductor substrate 101 and the N type epitaxial layer 103 is formed on the entire surface by a known method.
Next, a P type impurity element is diffused in a region of the N type epitaxial layer 103 surrounding the N ⁺ type buried layer 102 to form a P ⁺ type isolation diffusion layer 104 reaching the substrate 101. Then, in the N-type epitaxial layer 103, N ⁺
An N-type impurity element is diffused in the portion on the mold-buried layer 102 to form an N ⁺ -type diffusion layer 105. Then, 900 ℃,
Approximately 3000 Å after heat treatment for 80 minutes in H ₂ O atmosphere
Forming the oxide film 106. This N ⁺ type diffusion layer 105
The N ⁺ type buried layer 102 and the N type epitaxial layer 103 constitute an N type collector layer. Next, the same figure (b)
As shown in FIG. 5, photolithography and etching are performed to form an opening 106a in the portion of the oxide film 106 on the N ⁺ type buried layer 102, and then ¹¹ B ions (denoted by reference numeral 107) are implanted through the opening 106a. Then, the P ⁻ type active base 108 is formed on the surface of the N type epitaxial layer 103.
To form. Next, as shown in FIG.
A resist 110 is applied to the surface side of the substrate and photolithography is performed to form an opening 110a in a region of the resist 110 corresponding to the peripheral portion of the active base 108. ¹¹ B ions are implanted through this opening 110a to form a P ⁺ -type external base 111 at the peripheral portion of the active base 108 (note that the portion of the active base 108 left as the P ⁻ -type is referred to as “internal base”). ".). After removing the resist 110, as shown in FIG. 9D, the oxide film 1 is formed in the opening 106a.
12 is formed. Next, as shown in (e) of the figure, after forming an opening 112a in a portion of the oxide film 112 corresponding to the inner base 108, As ions are implanted through the opening 112a to form a surface of the inner base 108. Then, an N ⁺ type emitter region 114 is formed. After that, as shown in FIG. 3F, an oxide film 115 is provided on the entire surface by a known method,
Collector electrode 116, base electrode 117, emitter electrode 1
18 is formed.

In this vertical NPN transistor, the current amplification factor hFE is controlled by an internal base 108 having a low impurity concentration (P ⁻ ) and an external base 11 having a high impurity concentration (P ⁺ ) is used.
1 makes good ohmic contact with the base electrode 117.

[0004]

By the way, the vertical N
In the PN transistor, when the impurity concentration of the external base 111 is increased in order to reduce the base resistance, the P-type impurity element of the external base 111 is changed to the N-type epitaxial layer 10.
3 deeply and widely spread laterally. Therefore, the external base 111 is used as an emitter and the N-type epitaxial layer 10 is used.
There is a possibility that the current amplification factor hFE of the parasitic PNP transistor having the base 3 and the collector of the P ⁺ -type isolation diffusion layer 104 may increase, causing latch-up during operation.

In order to prevent this latch-up, conventionally, the distance between the external base 111 and the P ⁺ -type isolation diffusion region 104 (base width of the parasitic PNP transistor) is widened.
Furthermore, the external base 111 and the P ⁺ -type isolation diffusion region 10
A high-concentration N ⁺ type region is provided between
(Increase the base concentration of the transistor). In any case, it is necessary to widen the distance between the external base 111 and the P ⁺ -type isolation diffusion region 104, and in such a case, there is a problem that the size of the transistor becomes large and the cost increases.

Therefore, an object of the present invention is to increase the hFE of a parasitic transistor without increasing the size of the transistor.
Therefore, it is an object of the present invention to provide a vertical transistor that can be suppressed, and that operates stably at low cost, and a manufacturing method thereof.

[0007]

In order to achieve the above object, the vertical transistor of the present invention has a single crystal N-type collector layer and a predetermined P-type impurity element introduced into the surface of the N-type collector layer. A low impurity concentration internal base provided, a high impurity concentration external base provided by introducing the P-type impurity element into a region surrounding the periphery of the internal base, and a predetermined N-type on the surface of the internal base. In a vertical transistor having an emitter region provided by introducing an impurity element, a defective layer is provided by implanting an inert impurity element ion or an ion containing an inert impurity element in the composition into the surface of the external base. It is characterized by

Further, according to the method of manufacturing the vertical transistor of the present invention, a predetermined P-type impurity element is introduced into the surface of the single crystal N-type collector layer to form an internal base having a low impurity concentration. A vertical transistor in which the P-type impurity element is introduced into a region surrounding a peripheral portion to form an external base having a high impurity concentration, and then a predetermined N-type impurity element is introduced into a surface of the internal base to form an emitter region. In the manufacturing method of the above method, when the outer base is formed, the surface of the region is surrounded by implanting ions containing the P-type impurity element and the inert impurity element into the surface of the region surrounding the inner base. In addition, the defect layer is formed while the P-type impurity element is introduced.

The P-type impurity element is B and the inactive impurity element is F. When forming the external base, BF ₂ ions are implanted at a dose of 2 × 10 ¹⁵ ions / cm ² or more. Then, it is desirable that the B contained in the injected BF ₂ is subsequently annealed at a temperature of 1000 ° C. or lower to be activated.

Further, according to the method of manufacturing the vertical transistor of the present invention, a predetermined P-type impurity element is introduced into the surface of the single crystal N-type collector layer to form an internal base having a low impurity concentration. A vertical transistor in which the P-type impurity element is introduced into a region surrounding a peripheral portion to form an external base having a high impurity concentration, and then a predetermined N-type impurity element is introduced into a surface of the internal base to form an emitter region. In the manufacturing method, when the outer base is formed, the P-type impurity element ions and the inert impurity element ions are implanted into the surface of the region surrounding the periphery of the inner base, and the surface of the region is The feature is that a P-type impurity element is introduced and a defect layer is formed.

The P-type impurity element is B and the inactive impurity element is F. When the external base is formed, B ions are dosed at 2 × 10 ¹⁵ ions / cm ² or more,
F ions are implanted under the condition of a dose amount of 4 × 10 ¹⁵ ions / cm ² or more, and then the implanted B is 1000 ° C.
It is desirable to anneal and activate at the following temperatures.

[0012]

When a defect layer is formed by injecting an inert impurity element ion or an ion containing an inert impurity element into the surface of the external base, a defect layer is formed, and the existence of the defect layer causes the external base to serve as an emitter. The emitter injection efficiency of the parasitic PNP transistor is reduced. As a result, the current amplification factor hFE of the parasitic PNP transistor decreases, latchup does not occur during operation, and the operation becomes stable. Further, since the size of the transistor is not expanded, the cost does not increase. Therefore,
The vertical transistor of the present invention is manufactured at a lower cost than the conventional transistor. The defect layer is
Since it is formed in the region of the external base of the vertical transistor, it does not increase the collector-emitter leakage current or the collector-base leakage current of the vertical transistor.

BF ₂ ions, for example, are implanted into the surface of the external base (P ⁺ type diffusion layer) formed in the single crystal N type collector layer (N layer) under the condition of a dose amount of 2 × 10 ¹⁵ ions / cm ² or more. In this case, the surface of the P ⁺ type diffusion layer is made amorphous. Subsequently, when annealing is performed at a predetermined temperature (described later), a defect layer D is formed at the interface between the amorphous and the single crystal as shown in FIG.

FIG. 3 is a vertical NPN shown in FIGS. 6 and 7.
Acceleration energy of 30 ke on the transistor external base Bo
Dose amount and parasitic PN when BF ₂ ions are implanted at V
The relationship with the current amplification factor hFE of the P transistor is shown. Further, FIG. 4 shows the relationship between the dose amount and the sheet resistance Rs of the external base Bo. As can be seen from FIG. 3, in the region where the dose amount is 2 × 10 ¹⁵ ions / cm ² or more,
The hFE decreases as the impurity concentration increases (ordinarily, the hFE increases as the impurity concentration increases). It is considered that this is because the defect layer D is generated on the surface of the external base Bo. As shown in FIG. 5, when the acceleration energy of ion implantation is 30 keV, the depth of the defect layer D is 200-80.
It becomes 0Å. Further, as can be seen from FIG. 4, when the dose amount increases, the value of the sheet resistance Rs decreases. However, even if it is set to 2 × 10 ¹⁶ ions / cm ² or more,
The sheet resistance does not decrease due to the relationship of the solid solubility limit for the single crystal N-type collector layer (usually Si). Therefore, in reality, the dose amount of BF ₂ ions is 2 × 10 ¹⁵ to
The range is set to 2 × 10 ¹⁶ ions / cm ² .

After the ion implantation, annealing is usually performed to activate the implanted impurities. If the temperature of 1000 ° C. or less, the present inventor
It was confirmed that the defect layer D remained in the. However, in order to activate the injected impurities, the temperature is actually 700 to
Anneal in the range of 1000 ° C.

As an inert impurity element, B (boron) is used.
Similarly, when BF and fluorine (F) are individually ion-implanted, a defect layer is formed in the vicinity of the surface of the external base, as in the case of BF ₂ . However, since F ions have a smaller mass number than BF ₂ , a dose amount of 2 to 3 times or more is required to form a defect layer of the same degree as BF ₂ . The annealing temperature is 700 to 1 as in the case of BF _2.
It may be set in the range of 000 ° C.

[0017]

The vertical transistor of the present invention and the method for manufacturing the same will be described below in detail with reference to Examples.

It is assumed that the vertical NPN transistor shown in FIG. 2 (f) is manufactured. This vertical NPN transistor
A low impurity concentration internal base 8 provided on the surface of the collector layer 3, a high impurity concentration external base 11 provided in a region surrounding the periphery of the internal base 8, and an emitter provided on the surface of the internal base 8. It has a region 14.

First, as shown in FIG. 1A, an N ⁺ type buried layer 2 is provided in a predetermined region on the surface of a P type semiconductor substrate 1. In this N ⁺ type buried layer 2, for example, Sb ions are implanted through an oxide film (not shown) under the conditions of an acceleration energy of 60 keV and a dose of 3 × 10 ¹⁵ ions / cm ² , and then,
It is formed by annealing for activation at a temperature of 1150 ° C. for 500 minutes in an N ₂ atmosphere. Next, an N-type epitaxial layer 3 having a film thickness of 3.0 μm and a specific resistance of 1 Ω · cm is formed on the entire surface. Next, a P ⁺ type isolation diffusion layer 4 reaching the substrate 1 is formed in a region of the N type epitaxial layer 3 surrounding the N ⁺ type buried layer 2. The P ⁺ -type isolation diffusion layer 4 has an acceleration energy of ¹¹ B ions of 80 keV and a dose of 3 × 10 ¹⁵ ions / c through an oxide film (not shown).
It is formed by implanting under the condition of m ² and then performing annealing for activation at a temperature of 1150 ° C. for 300 minutes in an N ₂ atmosphere. Next, in the N-type epitaxial layer 3, N
^An N ⁺ type diffusion layer 5 is formed on the ⁺ type buried layer 2. In the N ⁺ type diffusion layer 5, for example, ³¹ P ions are implanted under the conditions of an acceleration energy of 80 keV and a dose of 4 × 10 ¹⁵ ions / cm ² , and then annealing for activation is performed at a temperature of 1.
It is formed by carrying out at 000 ° C. for 180 minutes in an N ₂ atmosphere. Then, heat treatment is performed in an atmosphere of H ₂ O at 900 ° C. for 80 minutes to form an oxide film 6 of about 3000 Å. The N ⁺ type diffusion layer 5, the N ⁺ type buried layer 2, and the N type epitaxial layer 3 form a collector layer.

Next, as shown in FIG. 3B, photolithography and etching are performed to form an opening 6a in the portion of the oxide film 6 on the N ⁺ type buried layer 2. After this, through this opening 6a, ¹¹ B ions (denoted by reference numeral 7)
Acceleration energy 50 keV, dose 3 × 10 ¹³ ions / c
It is injected under the condition of m ² to form P on the surface of the N-type epitaxial layer 3.
^- forming an active base 8 of the mold.

Next, as shown in FIG. 1C, a resist 10 is applied on the front surface side of the substrate 1 and photolithography is performed to form a resist 10 in a region corresponding to the peripheral portion of the active base 8. The opening 10a is provided. Through this opening 10a, BF ₂ ions (denoted by reference numeral 9) are accelerated with an energy of 30 k.
Implantation is performed under the conditions of eV and a dose amount of 3 × 10 ¹⁵ ions / cm ² to form a P ⁺ -type external base 11 on the peripheral portion of the active base 8 (note that the P ⁻ -type of the active base 8 remains. That part is called "internal base".)

After removing the resist 10, as shown in FIG. 2D, annealing for activating the impurities implanted into the external base 11 is performed at a temperature of 950 ° C. for 60 minutes and N ₂
Performed in an atmosphere, then 900 ° C. for 80 minutes, H ₂
Perform in an O atmosphere. As a result, the opening 6a has a thickness of about 30
The oxide film 12 of 00Å is formed and the external base 8
Defect layer 13 extending from the surface to a depth of 200 to 800 Å
To form.

Next, as shown in FIG. 1E, the oxide film 1
After providing an opening 12a in a portion corresponding to the inner base 8 of the No. 2, As ions are implanted through the opening 12a under the conditions of an acceleration energy of 50 keV and a dose amount of 5 × 10 ¹⁵ ions / cm ² , An N ⁺ type emitter region 14 is formed on the surface of the.

After that, as shown in FIG.
By the method, an oxide film 15 having a thickness of about 4000Å is provided on the entire surface. Subsequently, annealing is performed at a temperature of 920 ° C. for 60 minutes in an N ₂ atmosphere to activate the impurities in the emitter region 14. Finally, by a known method, the collector electrode 1
6, the base electrode 17 and the emitter electrode 18 are formed.

Thus, in this vertical NPN transistor, BF ₂ ions are implanted into the surface of the external base 11 to form the defect layer 13. The presence of this defect layer 13 can reduce the emitter injection efficiency of a parasitic PNP transistor having the external base 11 as an emitter, the N type epitaxial layer 3 as a base, and the P ⁺ type isolation diffusion layer 4 as a collector. Therefore, the current amplification factor hFE of the parasitic PNP transistor can be reduced. As a result, this vertical NPN transistor does not cause latch-up during operation and can operate stably. Further, since the size of the transistor is not expanded, the cost does not increase. Therefore, this vertical NPN transistor can be manufactured at lower cost than the conventional transistor. The defect layer 13 is the external base 11 of the vertical NPN transistor.
Since it is formed inside, the collector-emitter leakage current and the collector-base leakage current of this vertical NPN transistor are not increased.

In the above process, ¹¹ B ions and F ions may be used instead of BF ₂ ions. For example,
¹¹ B ion acceleration energy 10 keV, dose 3 × 10
Implantation is performed under the conditions of ¹⁵ ions / cm ² , and then F ions are implanted under the conditions of an acceleration energy of ¹⁵ keV and a dose of 6 × 10 ¹⁵ ions / cm ² . Also in this case, as in the case of BF ₂ ,
The defect layer 13 can be formed on the surface of the external base 11, and the vertical N
The operation of the PN transistor can be stabilized. The order of implanting ¹¹ B ions and F ions may be interchanged.

Further, the ionic species for forming the defect layer are F, Cl, Ar, Ne, BF, BF ₂ , BF ₃ , BCl, BC.
Either l ₂ or BCl ₃ may be used. However, the dose amount of ion implantation to the external base region 11 is set according to the mass number of the adopted ions.

[0028]

As is apparent from the above, the vertical transistor of the present invention is provided with a single crystal N-type collector layer and a low-density transistor provided by introducing a predetermined P-type impurity element into the surface of the N-type collector layer. An internal base having an impurity concentration, an external base having a high impurity concentration provided by introducing the P-type impurity element in a region surrounding the periphery of the internal base, and a predetermined N-type impurity element being introduced on the surface of the internal base. In the vertical transistor having the emitter region provided as described above, the surface of the external base is provided with a defect layer by injecting an inert impurity element ion or an ion containing an inert impurity element in the composition, The presence of this defect layer reduces the emitter injection efficiency of the parasitic PNP transistor having the external base as an emitter, and the current amplification factor hF thereof is reduced.
E can be reduced. Therefore, it is possible to prevent latch-up from occurring during operation, and it is possible to operate stably. Further, since the size of the transistor is not increased, the cost does not increase, and the transistor can be manufactured at lower cost than the conventional transistor.

Further, in the method of manufacturing a vertical transistor of the present invention, when the external base is formed, the P-type impurity element and the inactive impurity element have a composition on the surface of the region surrounding the periphery of the internal base. Implanting the containing ions,
Since the defect layer is formed while introducing the P-type impurity element on the surface of the region, it is possible to manufacture the above-described vertical transistor that operates stably and is inexpensive.

The P-type impurity element is B and the inactive impurity element is F. When forming the external base, BF ₂ ions are implanted under the condition of a dose amount of 2 × 10 ¹⁵ ions / cm ² or more. Then, if B contained in the implanted BF ₂ is subsequently annealed and activated at a temperature of 1000 ° C. or less, a desired defect layer can be left on the surface of the external base after the annealing.

Further, in the method for manufacturing a vertical transistor of the present invention, when the outer base is formed, the P-type impurity element ion and the inert impurity element ion are formed on the surface of the region surrounding the inner base. By implanting and introducing the P-type impurity element into the surface of the region and forming the defect layer, the stable operation as described above is achieved.
Moreover, an inexpensive vertical transistor can be manufactured.

The P-type impurity element is B and the inactive impurity element is F. When forming the external base, B ions are dosed at 2 × 10 ¹⁵ ions / cm ² or more,
F ions are implanted under the condition of a dose amount of 4 × 10 ¹⁵ ions / cm ² or more, and then the implanted B is 1000 ° C.
When annealed and activated at the following temperatures, a desired defect layer can be left on the surface of the external base after annealing.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a vertical transistor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a vertical transistor according to an embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a dose amount of an external base region and hFE of a parasitic PNP transistor.

FIG. 4 is a diagram showing a relationship between a dose amount of an external base region and a sheet resistance.

FIG. 5 is a diagram schematically showing a state in which a defect layer is formed on the surface of a P ⁺ diffusion layer.

FIG. 6 is a diagram showing a main part of a pattern of a vertical transistor to be manufactured.

FIG. 7 is a diagram showing a main part of a cross section of a vertical transistor to be manufactured.

FIG. 8 is a diagram illustrating a conventional method of manufacturing a vertical transistor.

FIG. 9 is a diagram illustrating a conventional method of manufacturing a vertical transistor.

[Description of Reference Signs] 1 P-type semiconductor substrate 2 N ⁺ type buried layer 3 N type epitaxial layer 4 P ⁺ type isolation diffusion layer 5 N ⁺ type diffusion layer 8 Internal base 11 External base 14 Emitter region

Claims (5)

[Claims] 1. A single crystal N-type collector layer, a low impurity concentration internal base provided by introducing a predetermined P-type impurity element into the surface of the N-type collector layer, and a region surrounding the periphery of the internal base. A vertical transistor having a high impurity concentration external base provided by introducing the P-type impurity element into the semiconductor substrate and an emitter region provided by introducing a predetermined N-type impurity element on the surface of the internal base, A vertical transistor characterized in that a defect layer is provided by implanting an inert impurity element ion or an ion containing an inert impurity element in a composition into a surface of an external base. 2. A predetermined P-type impurity element is introduced on the surface of the single crystal N-type collector layer to form an internal base having a low impurity concentration, and the P-type impurity element is formed in a region surrounding a peripheral portion of the internal base. Is formed to form an external base having a high impurity concentration, and then a predetermined N-type impurity element is introduced to the surface of the internal base to form an emitter region, wherein the external base is formed. At this time, ions containing the P-type impurity element and the inert impurity element in the composition are implanted into the surface of the region surrounding the inner base to introduce the P-type impurity element into the surface of the region. A method of manufacturing a vertical transistor, which comprises forming a defect layer. 3. The method of manufacturing a vertical transistor according to claim 2, wherein the P-type impurity element is B and the inactive impurity element is F, and BF ₂ ions are dosed when the external base is formed. A vertical transistor characterized in that it is implanted under the condition of an amount of 2 × 10 ¹⁵ ions / cm ² or more, and subsequently B contained in the implanted BF ₂ is annealed and activated at a temperature of 1000 ° C. or less. Manufacturing method. 4. A predetermined P-type impurity element is introduced into the surface of the single crystal N-type collector layer to form an internal base having a low impurity concentration, and the P-type impurity element is formed in a region surrounding a peripheral portion of the internal base. Is formed to form an external base having a high impurity concentration, and then a predetermined N-type impurity element is introduced to the surface of the internal base to form an emitter region, wherein the external base is formed. At this time, the P-type impurity element ions and the inert impurity element ions are implanted into the surface of the region surrounding the periphery of the internal base, and the P-type impurity element is introduced into the surface of the region and a defect layer is formed. A method of manufacturing a vertical transistor, which is characterized by forming the same. 5. The method of manufacturing a vertical transistor according to claim 4, wherein the P-type impurity element is B and the inactive impurity element is F, and a dose amount of B ions is formed when the external base is formed. Two
× 10 ¹⁵ ions / cm ² or more, F ion dose 4 × 1
A method for manufacturing a vertical transistor, which comprises implanting under a condition of 0 ¹⁵ ions / cm ² or more, and subsequently activating the implanted B by annealing at a temperature of 1000 ° C. or less.