JPS615568A - Manufacture of complementary mos integrated circuit - Google Patents

Abstract

PURPOSE:To greatly improve the latchup-withstanding capability by a method wherein an N<-> substrate containing a high concentration of oxygen is exposed to a high temperature for the diffusion outward of the contained oxygen and another stage of heat treatment follows for the generation of oxygen donors. CONSTITUTION:When an N<-> substrate 1 containing a high concentration of oxygen is exposed to a high temperature, of 1,150 deg.C for example, the contained oxygen is diffused outward and, when the substrate 1 is exposed to 450 deg.C for dozens of hours, oxygen donors are created. Few oxygen donors are created on the surface of the substrate 1 where oxygen is low in concentration. Oxygen is caused to be diffused outward before the formation of a P well 2. Conventional MOS- producing steps are followed, which terminate when metal is vapor-deposited for an electrode wiring 8. After the lower-temperature heat treatment for the creation of oxygen donors, the electrode wiring 8 is completed. In this design, for the same reason as the formation of an N<-> epitaxial layer on the N<-> substrate 1, the latchup-withstanding capability is enhanced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary MOS integrated circuit device (0MOSIC) K using an N substrate, and relates to a manufacturing method for increasing latch-up resistance by generating oxygen donors. It is something.

[Prior art]

Conventionally, a CMOSIC using an N substrate has the structure shown in FIG. Here, seven examples of inverters with basic circuits are taken as 0MOS.

In this figure, 1 is N-substrate, 2 is P-well, 3, s
', f are P+ diffusion layers, 4, 4' are N+ diffusion layers, 5 is gate oxide film, 6 is polycrystalline silicon, 7 is C'VD oxide film,
8 is the electrode wiring, IN is the input end, OUT is the output end, ■8B
, ■DD is a power supply. Also, 7rl is N channel M
OS transistor (Tr 2 is P-channel MOS) indicates run risk.

0MOSC has advantages such as low power consumption and large logic amplitude (large noise margin), and in VLSI, NM
It is expected to replace o8K.

However, in the 0MOS structure, a latch-up phenomenon is likely to occur due to parasitic silicon risk operation, and this has become a serious problem with miniaturization.

In FIG. 1, the cause of latch amplifier generation will be explained.

If a noise current of ■ enters from the output terminal OUT, holes are injected from the P diffusion layer 3', which is the drain of the P channel, and the lateral parasitic PNP transistor turns on, causing a comverter in the P fer 2. A current (hole) flows and the potential of the P shell 2 increases. At this time, P shell 2
When the potential of N-channel MOS) becomes higher than the diffusion potential, the source of the N-channel MOS) run lister Trl becomes forward biased, the vertical parasitic NPN) run lister is turned on, and a flefter current (electrons flow into the N- substrate 1, causing an N-
The potential of the substrate 1 drops, and the source (P diffusion layer 3) side of the P-channel MOS transistor (R2) becomes forward biased, and the parasitic PNP) run resistor turns on, causing the P-channel MOS transistor (R2) to become forward biased. Inject IC holes. In this way, if the positive feedback is not turned off and the power is not turned off, abnormal current will continue to flow between the power supplies VD, -V, and eventually destroy the IC.

On the other hand, when a noise current of 00 Vce enters the output terminal, electrons are injected from the N diffusion layer 4', which is the drain of the N-7 channel MOS transistor Trl, and the N-substrate 1
Since electrons enter K, a latch amplifier occurs for the same reason as above. As a method of increasing the latch amplifier withstand capability, based on the above principle, the structural parasitic PNP transistor and the vertical parasitic NPN
) There is a method to reduce the current amplification factor of the run lister, but
It is a well-known fact that this method has its limits as miniaturization progresses. On the other hand, as a method of suppressing fluctuations in the potential of the P shell 2 or the N− substrate 1, for example, as shown in FIG. and reverse conductive P diffusion layer 3'
' is provided and commonly connected to the N diffusion layer 4 (a common method is adopted).

In Figure 1, a common contact is not used on the source side of the P-channel MOS (MOS) run lister Tr2, that is, on the P diffusion layer 3 side, but generally a common contact is used to prevent latch failure. . However, for example, in static RAM, K cannot make common contact because the memory size is small, and the structure often becomes like the one shown in Figure 1. One of the reasons is that the chip resistance is low. There is. In addition, increasing the concentration of -P'7 L2 and the concentration of N-substrate 1 in order to prevent fluctuations in the potentials of P shell 2 and N-substrate 1 is also a means to prevent latch-up, but N-substrate 1 If the impurity concentration of P shell 2 is increased, it becomes necessary to increase the impurity concentration of P shell 2, and it is very difficult to control the threshold tlLvTn. To compensate for this drawback, there is a method of forming a 5K, KN-epitaxial layer 10 on a highly doped substrate 9, as shown in Figure 2, but the threshold value VTII varies due to autodoping caused by epitaxial growth 1RVC, and [Summary of the Invention] This invention has been made to eliminate the drawbacks of the conventional method as described above, and is a method for forming an epitaxial layer. Complementary MO can increase the concentration of the Nll substrate and leave the semiconductor surface at a low concentration without causing any damage, and the threshold value vT can be easily controlled and the launch amplifier withstand capability can be greatly increased.
The purpose is to provide S integrated circuits. An embodiment of the present invention will be described below with reference to the drawings.

[Embodiments of the invention]

N-substrate containing high concentration of oxygen, e.g. 1,8 at 20Ω
x 10"am-" (DM board YKm, e.g. 1150
When the heat treatment is performed at .degree. C., oxygen is diffused outward, resulting in an oxygen concentration profile as shown in FIG. When this f′L is heat-treated at a low temperature, for example, 450° C., for more than 10 to several tens of hours, oxygen donors of 1 to 3 There is almost no oxygen donor generated, and 2O2cmJ
The impurity concentration is equivalent to /C. (Fig. 3(b), (a) and (b) are busy).

This is 1. This means that the transistor can be formed in exactly the same way as a normal 70-. As the text suggests, oxygen donors disappear in a short time at temperatures above 500 to 550°C, or are stable unless the temperature is raised. In other words, the heat treatment to generate oxygen donors should be carried out as quickly as possible in subsequent processes, for example, immediately before electrode wiring, and thereafter should not be exposed to heat treatment at temperatures above 400°C7.
Since the process after metal vapor deposition for electrode formation satisfies the above requirements, there is no particular problem.

Specifically, before forming the P-well 2, oxygen is diffused outward, and then the metal for the electrode wiring B is vapor-deposited.

Up to this point, normal MOS processes are performed. After that, we generate oxygen donors through low-temperature heat treatment, then perform metal vapor deposition, patterning, and electrode placement! i! After forming 8, a bathivation process is performed. At this time, since no oxygen donors are generated on the shallowest surface of the back surface of the N-substrate 1 and the resistance is high, it is necessary to polish the back surface.

According to the above method, the latch-up resistance is increased for the same reason as the formation of the KN-epitaxial layer on the N-substrate 1, and a complementary MOS integrated circuit can be manufactured stably at low cost.

FIG. 4 shows a cross-sectional view of a complementary MOS integrated circuit according to the present invention, in which reference numeral 11 is a KN substrate that generates oxygen donors, and the other features are the same as in FIG. 1.

In the above embodiment, an N-well is not formed for the P-channel R%08) transistor, but it goes without saying that the same effect can be obtained even if an N-well is formed.

In addition, in the above embodiment, 1. Outward diffusion of oxygen is performed before forming the P7-c-hole, but normally, when forming the well, the well is kept at a high temperature for a long time, and the oxygen is sufficiently outwardly diffused. Therefore, the above objective may be achieved by low-temperature heat treatment alone.

〔Effect of the invention〕

As explained above, the present invention is directed to N containing highly concentrated oxygen.
- Diffusion of oxygen outward from the substrate at high temperature;
Since it involves a process of heat treatment at around ℃ for a long time to generate oxygen donors, a KN-epitaxial layer is formed on the N-substrate, similar to that of a roof tile, and impurities can be selectively concentrated only inside the N-substrate. Therefore, the launch-up resistance is large,
It does not involve major process changes (CMOSIC!
There are advantages that can be made.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional CMOS integrated circuit, Figure 2 is a cross-sectional view of a conventional CMOS integrated circuit.
FIG. 3(a) is a sectional view of a conventional CMOS integrated circuit on which an epitaxial layer is formed. (b) is a diagram showing the oxygen concentration and the distribution of oxygen donor generation, each (in) is a cross-sectional view of the N-substrate, and each (b) is a diagram showing the oxygen concentration and the oxygen donor amount profile. The figure is a cross-sectional view of a complementary MOS integrated circuit according to an embodiment of the present invention. In the figure, 1 is an N-substrate, 2 is a P-well, s, s',
s: is a P+ diffusion layer, 4 and 4' are N+ diffusion layers, 5 is a gate oxide film, 6 is polycrystalline silicon, 1 is a CVD oxide film, 8 is an electrode wiring, and 11 is an N substrate. In addition, the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa (2 others λ Figure 1 To!? Turtle Figure 3 (a) (a) (b) Procedural amendment (voluntary) Showa 6% July 26th 1, Incident Display Patent Application No. 104931/1982 2,
Title of the invention Manufacturing method 3 of complementary MOSII quadruple product circuit
, the person making the correction, 5. Column 6 of Detailed Description of the Invention in the Specification Subject to Amendment, Contents of Amendment (1) Insert ``, oxygen concentration'' next to ``at 20 Ω (to)'' on page 6, line 2 of the specification. “ (2) Similarly, “400℃” in line 18 of the 6th kan is changed to “450℃”.
℃”. That's all~

Claims (1)

[Claims] A step of outwardly diffusing oxygen from an N^-substrate containing a high concentration of oxygen at high temperature, providing at least a P-well, a P-channel MOS transistor in the N^-substrate, and an N-well in the P-well. A complementary type M characterized by including a step of forming a channel MOS transistor and a step of generating oxygen donors by heat treatment at around 450° C. for a long time.
A method for manufacturing an OS integrated circuit.