KR100233142B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100233142B1 KR100233142B1 KR1019920015235A KR920015235A KR100233142B1 KR 100233142 B1 KR100233142 B1 KR 100233142B1 KR 1019920015235 A KR1019920015235 A KR 1019920015235A KR 920015235 A KR920015235 A KR 920015235A KR 100233142 B1 KR100233142 B1 KR 100233142B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract 5
- 239000010410 layer Substances 0.000 claims description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LBDSXVIYZYSRII-IGMARMGPSA-N alpha-particle Chemical compound [4He+2] LBDSXVIYZYSRII-IGMARMGPSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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Abstract
본 발명은 BiCMOS소자의 제조방법으로 메모리 셀의 P-웰 하부에 고농도의 n형 매몰층을 형성하기 위해 에피택셜성장을 이중단계로 실시함으로써 메모리셀이 형성될 P-웰의 농도를 적정농도로 유지하면서도 n형 매몰층의 농도를 높일 수 있어 n형 매몰층의 고상확산(Solid State Diffusion) 및 오토도핑(Autodoping)등과 같이 매몰층 상부 영역으로 불순물이 이동하는 것을 최대한 억제하여 메모리 셀에 기억된 신호가 파괴되는 것을 방지할 수 있다.The present invention provides a method for manufacturing a BiCMOS device, and epitaxial growth is performed in two steps to form a high concentration n-type buried layer under the P-well of a memory cell, thereby appropriately adjusting the concentration of the P-well in which the memory cell is to be formed. While maintaining the concentration of the n-type buried layer, it is possible to increase the concentration of the n-type buried layer so that impurities such as solid state diffusion and autodoping are prevented from moving to the upper region of the buried layer to the maximum. The signal can be prevented from being destroyed.
Description
제1(a)도 내지 제1(h)도는 본 발명에 의한 BiCMOS소자의 제조방법을 나타낸 공정단면도.1 (a) to 1 (h) are process cross-sectional views showing a method for manufacturing a BiCMOS device according to the present invention.
제2도는 본 발명 및 종래기술에 의해 제조된 BiCMOS소자에 있어서 n형 매몰층의 농도분포를 나타낸 그래프.2 is a graph showing the concentration distribution of an n-type buried layer in BiCMOS devices manufactured by the present invention and the prior art.
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 바이 씨 모오스(BiCMOS)소자의 메모리셀(memory cell)하부의 매몰층을 고농도로 형성함으로써 메모리 셀에 기억된 신호가 파괴되는 현상을 방지할 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by forming a buried layer under a memory cell of a BiCMOS device at a high concentration, it is possible to prevent a signal stored in a memory cell from being destroyed. A method for manufacturing a semiconductor device.
CMOS소자는 초기에 시계용과 탁상계산기용 칩에서부터 출발하여 1M비트 램(RAM)에 이르기까지 빠른속도로 성장하고 있다. 초기에는 주로 알루미늄 게이트형이였으나, 80년 전후 폴리실리콘 게이트형으로 바뀌면서 고집적화가 가능함에 따라 메모리소자는 비약적으로 발전하게 되었다. 폴리실리콘 게이트는 NMOS형 메모리에 적합하여 그 기술을 확립하였는바, CMOS형 소자의 고잡음 마진, 저소비전력, 논리회로 설계의 용이성, 고속동작등 고밀도 메모리에 적합한 제특성이 주목되어 현재에는 폴리실리콘 게이트 CMOS형 메모리가 주류를 이루고 있으며, 오늘날에는 전 소자가 CMOS만으로도 가능하다고 할 수 있다.CMOS devices are growing at a rapid rate, beginning with chips for clocks and desktop calculators, down to 1M bit RAM. In the early days, mainly aluminum gate type, but since the integration into the polysilicon gate type around 80 years, the high-density integration of the memory device has been developed significantly. Polysilicon gates are suitable for NMOS type memory, and the technology has been established. Currently, polysilicon has been noted for its high noise margin, low power consumption, ease of logic circuit design, high-speed operation, etc. Gate CMOS memory is the mainstream, and today all devices can be made with CMOS alone.
이에 따라 복합 CMOS경항이 두드러지고 있는데, 예를들면 고속의 동작특성을 가진 바이폴라 트랜지스터와 CMOS트랜지스터를 적절하게 결합시킨 BiCMOS기술은 이미 SRAM(Static Random Access Memory)등에 적용되고 있다.As a result, complex CMOS conditions are prominent. For example, BiCMOS technology, which properly combines a bipolar transistor and a CMOS transistor with high-speed operation characteristics, has already been applied to static random access memory (SRAM).
일반적으로 BiCMOS소자는 반도체 기판상에 n형 매몰층을 형성하고, 그후 트윈(twin)매몰층 형성방법을 통해 n+매몰층 및 P 매몰층을 형성한 후, 기판전면에 에피택셜층을 성장시킨 다음, n-웰 및 P-웰을 형성한다.In general, a BiCMOS device forms an n-type buried layer on a semiconductor substrate, and then forms an n + buried layer and a P buried layer through a twin buried layer formation method, and then grows an epitaxial layer on the entire surface of the substrate. Next, n-wells and P-wells are formed.
이와같이 종래의 BiCMOS제조공정시 매몰층 및 에피택셜층 성장공정은 연속적으로 이루어지고 있다.As described above, the buried layer and the epitaxial layer growing process are continuously performed in the conventional BiCMOS manufacturing process.
이 방법으로 매몰층과 에피택셜층 성장을 실시하면, 저농도의 n형 매몰층 형성후 P형 매몰층을 형성하고 에피택셜 성장한 후 그 위에 P-웰을 형성하기 때문에 하부의 n형 매몰층의 고상 확산(Solid-state outdiffusion) 및 오토도핑(Autodoping)으로 인해 P-웰 형성시 n-형 역전층이 형성될 수도 있고, n형 매몰층이 저농도로 형성되므로 노이즈에 취약한 소자특성을 가지게 된다.When the buried layer and the epitaxial layer are grown in this way, the P-type buried layer is formed after the formation of the low concentration n-type buried layer, and after the epitaxial growth, the P-well is formed thereon. Due to the solid-state outdiffusion and autodoping, an n-type inversion layer may be formed during P-well formation, and an n-type buried layer is formed at low concentration, thereby having device characteristics vulnerable to noise.
메모리 셀의 P-웰 하부에 n-형 매몰층의 농도가 낮으면 입, 출력 단자를 통하여 언더숫(undershoot) 이나 α-파티클(particle)과 같은 노이즈가 발생되어 메모리 셀에 기억된 신호가 파괴되게 된다.If the concentration of the n-type buried layer below the P-well of the memory cell is low, noise such as undershoot or α-particle is generated through the input and output terminals, thereby destroying the signal stored in the memory cell. Will be.
예를들면, 입·출력 단자영역중 NMOS트랜지스터의 소오스 또는 드레인 영역인 n+확산층에서 언더숫(undershoot)이 발생하면 n+확산층과 P-웰을 통한 순방향 전류가 발생하게 되는데, 그 결과 소수 캐리어인 전자가 메모리 셀이 형성되어 있는 P-웰로 주입될때 저농도의 n형 매몰층이 소수캐리어를 충분히 억제해 줄 수 없어 P-웰내의 메모리 셀에 저장되어 있는 신호가 파괴될 수 있다.For example, the mouth, when the under numerical (undershoot) occurs in the n + diffusion layers of the source or drain region of the output terminal of the NMOS transistor region there is the forward current through the n + diffusion layer and the P- well occur, so that the minority carrier When phosphorus electrons are injected into the P-well in which the memory cell is formed, the low concentration n-type buried layer cannot sufficiently suppress the minority carrier, and thus a signal stored in the memory cell in the P-well may be destroyed.
그러므로, P-웰 하부의 n형 매몰층을 고농도로 형성할 필요가 있으나, 이 경우 상기 고상확산 및 오토도핑 현상이 더욱 심화되어 이후에 형성될 P-웰 영역의 농도를 조정하기가 어려우므로 n형 매몰층의 농도를 일정농도 이상 유지할 수 없다.Therefore, although it is necessary to form the n-type buried layer under the P-well at a high concentration, in this case, since the solid phase diffusion and autodoping phenomenon are further intensified, it is difficult to adjust the concentration of the P-well region to be formed later. The concentration of the mold investment layer cannot be maintained above a certain concentration.
따라서, 본 발명은 상기한 종래 BiCMOS소자의 제조방법에 의한 제반 문제점을 해결하기 위한 것으로, 메모리셀 하부영역에 고농도의 n형 매몰층을 형성하여 입, 출력 단자를 통한 노이즈를 방지할 수 있는 BiCMOS소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve all the problems caused by the conventional manufacturing method of the BiCMOS device, BiCMOS that can prevent the noise through the input and output terminals by forming a high concentration n-type buried layer in the lower region of the memory cell Its purpose is to provide a method for manufacturing a device.
상기한 목적을 달성하기 위한 본 발명은 P-웰 영역하부의 n형 매몰층 형성시 에피택셜 성장을 두번 실시함으로써 적정농도의 n형 매몰층 및 P-웰을 갖는 BiCMOS소자를 형성하는 것을 특징으로 한다.The present invention for achieving the above object is characterized by forming a BiCMOS device having an n-type buried layer and P-well of appropriate concentration by performing epitaxial growth twice when forming the n-type buried layer under the P-well region do.
이하, 첨부한 제1(a)도 내지 제1(h)도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 1 (a) to 1 (h).
먼저, 제1(a)도에 도시한 바와 같이, 종래의 제조방법과는 달리, 반도체 기판(1)상에 n매몰층(2)을 형성한 후 약 0.5㎛ 정도의 진성(Intrinsic) 에피택셜층(E1)을 먼저 성장시킨 후, 제1(b)도에 도시한 것과 같이 통상의 트윈(twin) 매몰층 형성방법으로 n+매몰층(3) 및 P매몰층(4)을 형성시킨 후 원하는 두께의 에피택셜층(E2)을 형성시킨다. 이와같이 진성 에피택셜층(E1)을 먼저 성장시킴으로써 n매몰층(2)의 고상확산 및 오토도핑이 진행되므로 그후에 형성될 n+매몰층(3)과 P매몰층(4)의 농도에 영향을 미치지 않게 된다. 이후 공정은 제1(c)도에서와 같이, 종래의 BiCMOS소자의 제조방법과 동일하게, n-웰(5) 및 P-웰(6)을 상기 에피택셜층(E2)내에 형성한다. 이어서 제1(d)도에 나타낸 것과 같이 LOCOS(Local Oxidation of Silicon)산화방법으로 상기 각 웰의 경계 영역에 해당하는 기판전면에 필드 산화막(7)을 성장시킨 후 바이폴라 트랜지스터의 n+싱크(8)를 형성한다. 그 다음 CMOS영역의 기판상부에 게이트 절연막(9)을 중간층으로 하는 MOS용 게이트(10)와, 메모리 셀 영역의 상부에 NMOS 트랜지스터와 NMOS트랜지스터를 연결해주는 베리드 콘택용 내부연결선(도시되지 않음)을 각각 형성한 다음, LDD(Lightly doped drain)구조를 형성하기 위해 n형 이온을 전면에 걸쳐 이온주입한 후 상기 기판전면에 산화막(11)을 형성한다.First, as shown in FIG. 1 (a), unlike the conventional manufacturing method, after forming the n buried layer 2 on the semiconductor substrate 1, an intrinsic epitaxial of about 0.5 μm After growing the shir layer E1 first, and then forming the n + buried layer 3 and the P buried layer 4 by the conventional twin buried layer forming method as shown in FIG. An epitaxial layer E2 of a desired thickness is formed. By growing the intrinsic epitaxial layer E1 in this manner, the solid phase diffusion and autodoping of the n buried layer 2 proceed, so that the concentration of the n + buried layer 3 and the P buried layer 4 to be formed thereafter is not affected. Will not. Subsequently, the n-well 5 and the P-well 6 are formed in the epitaxial layer E2 in the same manner as in the conventional BiCMOS device manufacturing method, as shown in FIG. 1 (c). Subsequently, as shown in FIG. 1 (d), a field oxide film 7 is grown on the entire surface of the substrate corresponding to the boundary region of each well by LOCOS (Local Oxidation of Silicon) oxidation method, and then n + sink 8 of the bipolar transistor is formed. ). Next, an MOS gate 10 having a gate insulating film 9 as an intermediate layer on the substrate of the CMOS region, and an internal connection line for a buried contact connecting the NMOS transistor and the NMOS transistor to the upper portion of the memory cell region (not shown). After the formation of each, and then implanted n-type ions across the entire surface to form a lightly doped drain (LDD) structure, the oxide film 11 is formed on the entire surface of the substrate.
그 다음 제1(e)도에 도시한 바와 같이 반응성 이온식각(Reactive Ion Etching ; RIE)에 의한 이방성 식각에 의해 상기 산화막(11)을 식각하여 상기 게이트(10) 측벽에 산화막 스페이서(12)를 형성한 다음, 고농도의 n형이 온 및 P형 이온을 각각 주입시켜 NMOS트랜지스터의 n+소오스/드레인 영역(13) 및 메모리 셀 영역의 n+소오스/드레인 영역(13a)과, PMOS트랜지스터의 P+소오스/드레인 영역(14)을 형성한다.Next, as shown in FIG. 1 (e), the oxide layer 11 is etched by anisotropic etching by reactive ion etching (RIE) to form an oxide spacer 12 on the sidewall of the gate 10. form, and then, P of the high concentration of n-type is turned on and the P-type implanting ions respectively to the NMOS transistor n + source / drain regions 13 and the memory cell region of the n + source / drain regions (13a) and, PMOS transistor + Source / drain regions 14 are formed.
이때 고농도의 P형 이온주입시 바이폴라 트랜지스터의 외인성 베이스 영역(15)이 동시에 형성된다.At this time, the exogenous base region 15 of the bipolar transistor is simultaneously formed at the time of high concentration of P-type ion implantation.
그 다음 제1(f)도에서와 같이 P형의 이온을 재주입시켜 바이폴라 트랜지스터의 베이스영역(15a)을 형성하고 전면에 산화막(16)을 형성한 후 바이폴라 트랜지스터의 에미터 영역이 될 부분에 윈도우를 연다음, 다결정 실리콘(18)과 텅스텐 실리사이드(18a)를 형성한 후 열처리하여 에미터(17) 영역을 형성하고 상기 다결정실리콘(18)과 텅스텐 실리사이드(18a)를 패터닝하여 에미터전극을 형성하며, 그 다음 제1(g)도에 도시한 바와 같이 전면에 걸쳐 층간절연막(19)을 형성한 후 윈도우를 연 다음, 다결정 실리콘 패턴(20)을 형성한 후 메모리 셀의 로드저항(20a)영역을 제외한 상기 다결정실리콘 패턴(20)영역에 이온을 주입하여 내부연결선과 연결한다.Then, as shown in FIG. 1 (f), the base region 15a of the bipolar transistor is formed by re-injecting the ions of P type, and the oxide film 16 is formed on the entire surface of the bipolar transistor. After the window is opened, polycrystalline silicon 18 and tungsten silicide 18a are formed and then heat treated to form an emitter 17 region, and the polycrystalline silicon 18 and tungsten silicide 18a are patterned to form an emitter electrode. Next, as shown in FIG. 1 (g), the interlayer insulating film 19 is formed over the entire surface, the window is opened, the polycrystalline silicon pattern 20 is formed, and then the load resistance 20a of the memory cell is formed. The ion is implanted into the polysilicon pattern 20 region except for the region to be connected to the internal connection line.
그후 제1(h)도에서와 같이 층간 절연막(21)을 형성한 후 통상의 사진식각 및 금속배선공정으로 금속단자(22)를 형성한다.Thereafter, as shown in FIG. 1 (h), the interlayer insulating film 21 is formed, and then the metal terminal 22 is formed by a normal photolithography and metal wiring process.
상기 제조방법에 의한 본 발명의 BiCMOS소자와 종래기술에 의한 BiCMOS소자의 기판(1), n형 매몰층(2) 및 P형 매몰층(4)의 농도분포를 비교하여 보면, 제2도에 나타낸 바와 같이 종래의 BiCMOS소자(A)는 메모리셀 하부의 n형 매몰층(2)이 저농도로 형성되어 있으며, 본 발명에 의한 BiCMOS소자(B)는 고농도의 n형 매몰층(2)을 형성하면서도 이후에 형성될 P-웰의 농도를 일정하게 유지할 수 있다. 즉, 본 발명에 의한 BiCMOS소자의 제조방법은 n형 매몰층 형성 후 일정두께의 진성 에피택셜층을 성장시키고, n+매몰층 및 P-매몰층을 형성한 후 원하는 두께의 에피텍셜층을 다시 형성시킨 후, n-웰 및 P-웰을 형성하는 이중 에피택셜 성장으로 n형 매몰층 상부에 형성될 P-웰에 영향을 미치지 않으면서도 n형 매몰층의 농도를 충분히 높일 수 있어 입,출력단자를 통한 메모리 셀의 기억신호가 파괴되는 것을 방지할 수 있다.The concentration distributions of the substrate 1, the n-type buried layer 2 and the P-type buried layer 4 of the BiCMOS device of the present invention by the above-described manufacturing method and the BiCMOS device of the prior art are shown in FIG. As shown, in the conventional BiCMOS device A, the n-type buried layer 2 under the memory cell is formed at a low concentration, and the BiCMOS device B according to the present invention forms the n-type buried layer 2 having a high concentration. While maintaining the concentration of the P-well to be formed later. That is, in the method of manufacturing a BiCMOS device according to the present invention, after forming an n-type buried layer, an intrinsic epitaxial layer having a predetermined thickness is grown, an n + buried layer and a P-buried layer are formed, and an epitaxial layer having a desired thickness is again formed. After the formation, the double epitaxial growth forming the n-well and P-well can sufficiently increase the concentration of the n-type buried layer without affecting the P-well to be formed on the n-type buried layer. The memory signal of the memory cell through the terminal can be prevented from being destroyed.
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