JPH05206388A - Integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the speed of a BiCMOS integrated circuit and to raise the level of integration by adopting external collector structure capable of facilitating to lower the collector resistance and raising the degree of integration, even if the temperature lowers in the course of a process. CONSTITUTION:The gate electrode of a MOS transistor is composed of polycrystalline silicon 7A and a W silicide film 9. And concerning to the collector drawing-out part of a bipolar transistor, the W silicide film 9 is directly formed on the N<+>-type collector drawing-out region 8 provided so as to reach an N<+>-type buried region 2. The N<+>-type collector drawing-out region 8 is formed by high-energy ion implantation, and it becomes possible to lower the collector resistance since the surface density becomes much higher at the time of phosphorus diffusion into the polycrystalline silicon 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a manufacturing method thereof, and more particularly to a structure and a forming method of a collector extraction region of a bipolar transistor in BiCMOS.

[0002]

2. Description of the Related Art A conventional BiCMOS integrated circuit will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view of an NPN bipolar transistor and a PMOS transistor.
The case where the collector of the N bipolar transistor and the N well of the PMOS transistor are connected is shown.

First, as shown in FIG. 4A, an N ⁺ type buried region 2 is selectively provided on a P type silicon substrate 1 and then N type
The type epitaxial layer 3 is formed. After that, an N-type impurity is introduced to form an N well 4 and then a field oxide film 5 is formed by a selective oxidation method. Then, after performing necessary channel doping on the MOS transistor, a gate oxide film 6 is formed. Then, for example, a photoresist film 10D is formed as a mask material and patterned, and then the gate oxide film 6 on the collector extraction region is removed using the photoresist film 10D as a mask.

Next, as shown in FIG. 4B, after removing the photoresist film 10D, a polycrystalline silicon film is deposited on the entire surface, and then phosphorus is diffused on the entire surface. By this operation, the polycrystalline silicon film 7C becomes N type, and at the same time, the N ⁺ type collector extraction region 8 is formed. Next, after depositing the W silicide film 9, the collector lead-out region and the gate electrode formation region are masked with the photoresist film 10E, and the W silicide film 9 and the N ⁺ -type polycrystalline silicon film 7C are patterned.

Next, as shown in FIG. 4C, a P-type base region 11 and a P-type LDD boron region 12 are formed, a side oxide film 13 is formed on the side surface of the gate electrode, and a P ⁺ -type source / drain is formed. 14 and graft base 15 formation, oxide film 16
, An emitter contact opening, a polycrystalline silicon film 17 and an emitter 18 are formed to complete the basic structure of the NPN bipolar transistor and the PMOS transistor.

[0006]

DISCLOSURE OF THE INVENTION The above-mentioned conventional BiC
In the MOS integrated circuit, the collector extraction region 8 is formed by the direct contact method by diffusion of phosphorus from the polycrystalline silicon film 7C for forming the gate electrode. In this direct contact method, since the W silicide film 9 having a low resistance is provided on the collector region, it is possible to reduce the contact size on the collector.
This greatly contributes to high integration of the iCMOS integrated circuit.

Diffusion of phosphorus into the polycrystalline silicon film 7C for the gate electrode is usually performed in the range of 850 to 900 ° C.
The heat treatment after phosphorus diffusion is 0.8 μm rule BiCMOS
The maximum temperature in an integrated circuit is about 950 ° C, which results in N ⁺
The type collector lead-out region 8 is pressed toward the N ⁺ type buried region 2 to reduce the collector resistance. However, as the BiCMOS integrated circuit becomes faster and more highly integrated, the maximum heat treatment temperature is 90 because a shallow junction is formed.
When the temperature is suppressed to 0 ° C. or less, the distance between the N ⁺ type collector extraction region 8 and the N ⁺ type buried region 2 is large at a practical thickness of 1.0 to 1.5 μm of the N type epitaxial layer 3. , The collector resistance increases significantly. For example, when the maximum heat treatment temperature is lowered from 950 ° C. to 900 ° C., the collector resistance increases about four times under the same transistor forming conditions.

In order to avoid this, a method of performing phosphorus ion implantation using the photoresist film 10D as a mask in the step of FIG. 4A can be considered. However, when the photoresist film 10D is removed after the ion implantation, The damage or impurities are introduced into the gate oxide film 6, or the accelerated oxidation of the silicon doped with phosphorus in the initial stage of the growth of the polycrystalline silicon film 7C forms a silicon oxide film with a thickness of several nm. There is a problem that the contact resistance becomes large.

Further, in the above manufacturing method, the gate oxide film 6 is formed.
Since many manufacturing steps are required until the polycrystalline silicon film 7C is grown after the formation, there is a problem that the reliability of the gate oxide film 6 is lowered.

[0010]

In the integrated circuit device of the first invention, a gate electrode formed on a semiconductor substrate via a gate oxide film is composed of a polycrystalline silicon film and a metal silicide film formed thereon. And a high-concentration buried layer provided on the semiconductor substrate, a high-concentration collector extraction region provided in an epitaxial layer on the high-concentration buried layer and in contact with the high-concentration buried layer, and And a bipolar transistor having a metal silicide provided in contact with the surface of the concentration collector extraction region.

In the integrated circuit device of the second invention, a step of forming a high-concentration buried layer on a semiconductor substrate and then forming an epitaxial layer on the entire surface, and a step of forming a field oxide film on this epitaxial layer are performed. A step of forming a gate oxide film in the element formation region, a step of forming a polycrystalline silicon film on the entire surface and then patterning with a mask layer to remove the polycrystalline silicon film on the collector extraction region, and a step of using the mask layer A step of introducing an impurity into the collector extraction region to form a high concentration collector extraction region in contact with the buried layer; and removing the gate oxide film and the mask layer on the collector extraction region, and then forming a metal silicide film on the entire surface. Forming a gate electrode forming region and the collector lead-out region by patterning the metal silicide film and the polycrystalline silicon film. It is intended to include the step of leaving the band.

[0012]

The present invention will be described below with reference to the drawings. 1 and 2 are sectional views of a semiconductor chip for explaining the first embodiment of the present invention.

First, as shown in FIG. 1 (a), an N ⁺ type buried with a sheet resistance of 10 to 30 Ω / □ is formed on a P type silicon substrate 1 containing boron (B) of about 1 × 10 ¹⁵ cm ^-3. After selectively providing the region 2, the N-type epitaxial layer 3 containing 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ of phosphorus is grown at a temperature of 1000 to 1150 ° C. Next, acceleration voltage 100 to 20
After the N well 4 is selectively formed by phosphorus ion implantation with 0 kv and a dose amount of 3 to 8 × 10 ¹² cm ^-2 , a field oxide film having a thickness of about 600 nm is formed by a selective oxidation method using a silicon nitride film and polycrystalline silicon. 5 is formed.

Next, as shown in FIG. 1B, channel doping of the MOS transistor is performed. For example, for the N well 4 in the figure, an acceleration voltage of 10 to 20 kv and a dose of 5
Ion implantation of boron of × 10 ^{11 to} 5 × 10 ¹² cm ^-2 is performed. Next, the silicon surface is oxidized at about 700 to 800 ° C. to form the gate oxide film 6 with a thickness of about 10 nm. Further, polycrystalline silicon 7 having a thickness of about 150 nm is deposited on the entire surface.

Next, a photoresist film 10A having a thickness of 2 to 4 μm is formed as a mask material, and an opening is provided in the collector extraction region. Then, after etching the polycrystalline silicon film 7 using the photoresist film 10A as a mask,
Acceleration voltage 200 kv to 1 MV, dose amount 10 ^{14 to} 510
Phosphorus ion implantation of ¹⁵ cm ^-2 and acceleration voltage 100 to 30
Ion implantation of phosphorus is performed at ⁰ kv and a dose amount of about 5 × 10 ¹⁴ cm ⁻² to form the N ⁺ type collector extraction region 8 so as to reach the N ⁺ type buried region 2.

Next, as shown in FIG. 1C, after removing the photoresist 10A, the gate oxide film 6 on the collector extraction region is removed. Then, phosphorus is diffused on the entire surface at about 850 ° C. At this time, the polycrystalline silicon film 7 becomes the N ⁺ type polycrystalline silicon film 7A, and the phosphorus concentration near the surface of the N ⁺ type collector extraction region 8 is further increased.

Next, after removing the oxide film at the time of phosphorus diffusion with a hydrogen fluoride solution, a W silicide film 9 having a thickness of 100 to 200 nm is deposited on the entire surface. Next, a photoresist film 10B is formed and then patterned, and is left on the gate electrode formation region and the collector extraction region, and then the W silicide film 9 and the polycrystalline silicon film 7A are etched using this photoresist film 10B as a mask.

As a result, as shown in FIG. 2A, the MOS
A polycide electrode composed of an N ⁺ type polycrystalline silicon film 7A and a W silicide film 9 is provided on the gate region of the transistor, and a W silicide film 9 is provided on the collector extraction region 8. This N ⁺ type collector lead-out region 8 and W
The silicide film 9 exhibits good ohmic characteristics.

Next, after removing the photoresist film 10B, an accelerating voltage of 10 to 30 kv and a dose of 1 to 3 × 10 ¹³ cm ^-2.
P type base 11 is formed by ion implantation of boron, and the acceleration voltage is 10 to 20 kv and the dose is 1 × 10 ^13.
The LDD boron region 12 is formed by implanting boron ions of about cm ⁻² .

Next, as shown in FIG. 2B, the side oxide film 13 is formed on the side surface of the gate electrode by the same operation as in the conventional case. Next, acceleration voltage 50-80kv, dose 1x1
By ion implantation of BF ₂ of 0 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² ,
A P ⁺ type source / drain 14 and a graft base 15 are formed. Then, the oxide film 1 having a thickness of about 100 nm is formed on the entire surface.
After depositing 6, the emitter contact portion is opened to form a polycrystalline silicon film 17 for emitter with a thickness of about 200 nm.
Is deposited. Next, for example, an impurity is introduced into the polycrystalline silicon film 17 by ion implantation of arsenic with an acceleration voltage of 70 kv and a dose of about 1 × 10 ¹⁶ cm ^-2 , and heat treatment at 850 to 900 ° C. is performed to form an emitter 18 by diffusion of arsenic. The polycrystalline silicon film 17 is patterned.

Insulation film formation, contact opening Al
The electrodes of each element made of SiCu / TiN / Ti are formed, and the PMOS transistor and N having the desired characteristics are formed.
Complete the PN bipolar transistor.

In the first embodiment, the method for manufacturing the NPN bipolar transistor and the PMOS transistor has been described as an example. However, an NMOS transistor having an N type polycide electrode made of N ⁺ type polycrystalline silicon and W silicide and a complementary MOS transistor. The present invention can be similarly applied to a combination of a transistor and an NPN bipolar transistor.

Next, a second embodiment will be described with reference to FIGS. 3 (a) and 3 (b). The second embodiment is an example of a method of forming a P-type polycide gate structure PMOS transistor and an NPN bipolar transistor.

First, the same steps as those in the first embodiment are performed and the process shown in FIG.
The substrates up to (b) are formed. However, as the mask material, a photoresist film and aluminum having a thickness of 1 to 2 μm patterned by the photoresist film are used. After the phosphorus ion implantation in FIG.
v, arsenic ion implantation with a dose amount of 10 ¹⁵ to 10 ¹⁶ cm ⁻² is added. Next, after removing the mask material, the gate oxide film 6 on the collector extraction region which is not covered with the polycrystalline silicon 7 is removed.

Next, as shown in FIG. 3A, after a W silicide film 9 having a thickness of about 100 to 200 nm is formed on the entire surface,
W using the patterned photoresist film as a mask
The silicide film 9 and the polycrystalline silicon film 7 are etched to remove the photoresist film. Next, the same operation as in the first embodiment is performed to form the base 11 and the LDD boron region 12.

Next, as shown in FIG.
After depositing the oxide film 16 of about m, the polycrystalline silicon film 17 for the emitter and the emitter 18 are formed by the same process as in the first embodiment.
To form. Next, the oxide film 16 is etched back to leave the oxide film 16 on the side wall of the polycide electrode. Next, using the photoresist film 10C as a mask, an acceleration voltage of 40 to 70 kv,
By ion implantation of BF _{2 with} a dose amount of 10 ¹⁵ to 10 ¹⁶ cm ⁻² , a P ⁺ type source / drain 14 and a graft base 1 are formed.
5 is formed. At this time, the polycrystalline silicon film 7 becomes the P ⁺ -type polycrystalline silicon 7B.

After that, similarly to the first embodiment, an insulating film is formed, a contact hole is formed, and an electrode is formed to complete a PMOS transistor and an NPN bipolar transistor having desired characteristics.

In the second embodiment, the combination of the PMOS transistor and the NPN bipolar transistor has been described, but the same applies to the NMOS transistor. The gate electrode of the NMOS transistor is a polycide composed of an N ⁺ type polycrystalline silicon film and a W silicide film. Further, the polycrystalline silicon 7 becomes N ⁺ type polycrystalline silicon due to the ion implantation of arsenic when forming the source and drain of the NMOS transistor.

In this embodiment, it is possible to provide a P-type polycide gate for the PMOS transistor and an N-type polycide gate for the NMOS transistor. Further, the contact property between the N ⁺ type collector extraction region 8 and the W silicide film 9 exhibits good ohmic property because shallow ion implantation is performed with arsenic.

[0030]

As described above, the integrated circuit device of the present invention has an MO having a polycide gate electrode composed of a polycrystalline silicon film and a metal silicide layer provided thereon.
The bipolar transistor has an S-transistor, a high-concentration collector extraction region provided so as to reach the high-concentration collector buried region, and a collector extraction structure including a metal silicide layer provided in contact with the surface of the extraction region. .. In this structure, the high-concentration collector extraction region is provided independently of the manufacturing process of the MOS transistor and in a consistent process, so that the manufacturing temperature is lowered as the MOS transistor becomes faster and more highly integrated. It is possible to reduce the collector resistance of the bipolar transistor independently of the performance of the MOS transistor.

Further, in the present invention, after forming the high concentration collector extraction region, the metal silicide film is provided thereon. For example, since the W silicide film is grown at a low temperature of about 300 ° C., there is no problem of the interfacial oxide film as seen when growing the polycrystalline silicon film. Therefore, the ohmic contact between the metal silicide film and the high concentration collector extraction region becomes very good.

When a BiCMOS integrated circuit of 0.6 μm rule is formed by using the technique of the present invention, the collector resistance of the bipolar transistor formed by the conventional technique is 300Ω.
However, the collector resistance is reduced to 50Ω.

In implementing the present invention, the number of steps added to the prior art is small, and a new masking step is not required. Moreover, since the performance of the bipolar transistor is significantly improved as described above, the technique of the present invention is
iCMOS integrated circuit, especially BiC that requires high integration
It greatly contributes to high speed and high integration of MOS logic circuits.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a conventional method for manufacturing an integrated circuit device.

[Explanation of symbols]

1 P-type silicon substrate 2 N ⁺ type buried layer 3 N type epitaxial layer 5 Field oxide film 6 Gate oxide film 7, 7A to 7C Polycrystalline silicon film 8 N ⁺ type collector extraction region 9 W silicide film 10A to 10E Photoresist Film 11 Base 12 LDD Boron Region 13 Side Oxide Film 14 Source / Drain 15 Graft Base 16 Oxide Film 17 Polycrystalline Silicon Film 18 Emitter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location // H01L 29/46 D 7738-4M T 7738-4M

Claims (2)

[Claims] 1. A MOS transistor having a polyimide structure in which a gate electrode formed on a semiconductor substrate via a gate oxide film is composed of a polycrystalline silicon film and a metal silicide film formed on the polycrystalline silicon film, and a MOS transistor provided on the semiconductor substrate. High-concentration buried layer, a high-concentration collector extraction region provided in the epitaxial layer on the high-concentration buried layer and in contact with the high-concentration buried layer, and a metal silicide provided in contact with the surface of the high-concentration collector extraction region An integrated circuit device comprising: a bipolar transistor having: 2. A step of forming a high-concentration buried layer on a semiconductor substrate and then forming an epitaxial layer on the entire surface, and a step of forming a field oxide film on the epitaxial layer and then forming a gate oxide film in the element formation region. Forming step, forming a polycrystalline silicon film on the entire surface, patterning using a mask layer to remove the polycrystalline silicon film on the collector extraction region, and introducing impurities into the collector extraction region using the mask layer Forming a high concentration collector extraction region in contact with the buried layer; forming a metal silicide film on the entire surface after removing the gate oxide film and the mask layer on the collector extraction region; Patterning the silicide film and the polycrystalline silicon film and leaving them on the gate electrode formation region and the collector extraction region. And a method of manufacturing an integrated circuit device.