KR930004298B1 - Making method of npn type transistor - Google Patents
Making method of npn type transistor Download PDFInfo
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- KR930004298B1 KR930004298B1 KR1019900019713A KR900019713A KR930004298B1 KR 930004298 B1 KR930004298 B1 KR 930004298B1 KR 1019900019713 A KR1019900019713 A KR 1019900019713A KR 900019713 A KR900019713 A KR 900019713A KR 930004298 B1 KR930004298 B1 KR 930004298B1
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- South Korea
- Prior art keywords
- layer
- forming
- epi
- epi layer
- poly
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 33
- 238000011109 contamination Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000002054 transplantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Abstract
Description
제1도는 종래 NPN형 트랜지스터의 제조공정도.1 is a manufacturing process diagram of a conventional NPN transistor.
제2도는 본 발명에 의한 NPN형 트랜지스터의 제조공정도.2 is a manufacturing process diagram of an NPN transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : SiO2층1 substrate 2 SiO 2 layer
3 : P-EPI층 5 : P-POLY층3: P-EPI layer 5: P-POLY layer
6 : 활성층 7' : 2차 EPI층6: active layer 7 ': secondary EPI layer
8 : 산화막 9 : 폴리층8: oxide film 9: poly layer
본 발명은 NPN형 트랜지스터의 제조방법에 관한 것으로, 특히 폴리(POLY)를 이용하여 절연층을 형성하고 2차 EPI층과 셀프얼라인(SELF ALINE)기법을 사용하여 초고속 집적회로에 적합하도록 한 NPN형 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an NPN transistor, in particular an NPN formed of an insulating layer using poly (POLY) and adapted to a high speed integrated circuit using a secondary EPI layer and a self-aligned (SELF ALINE) technique. It relates to a method of manufacturing a type transistor.
종래 NPN형 트랜지스터를 제조함에 있어서는, P형이나 N형 기판(1)위에 EPI층(2)을 형성[제1(a)도]하고, 버리드층(BURID LAYER)(3) 및 절연층(4)을 확산[제1(b)도] 시킨 다음, 활성영역(ACIVE REGION)(5)층을 형성[제1(c)도]하여 제1(d)도와 같은 단면의 NPN형 트랜지스터를 얻는 것이었다.In manufacturing a conventional NPN transistor, an EPI layer 2 is formed on the P-type or N-type substrate 1 (also referred to as first (a)), and the buried layer (BURID LAYER) 3 and the insulating layer 4 are formed. ) Is diffused (first (b)), and then an active region (5) layer is formed (first (c)) to obtain an NPN transistor having the same cross section as the first (d). .
그러나 이러한 종래의 NPN형 트랜지스터의 제조방법에 있어서는 오버 에치(OVER ETCH) 및 확산시 소스(SOURCE)로 인한 오염등의 공정불량이 발생되기 쉬우며, 크기의 소형화가 어렵게 되는 문제점이 있었다.However, the conventional NPN transistor manufacturing method has a problem in that process defects such as contamination due to OVER ETCH and SOURCE during diffusion are likely to occur, and miniaturization of size is difficult.
따라서 본 발명의 목적은, 폴리를 이용하여 절연층을 형성하고 2차 EPI층과 셀프얼라인 기법을 이용하여 오버 에치나 확산시 오염을 방지하고 크기를 소형화할 수 있어 초고속 집적회로에 적합한 NPN형 트랜지스터의 제조방법을 제공하려는 것이다.Accordingly, an object of the present invention is to form an insulating layer using poly, and to prevent contamination during over-etching or diffusion by using a secondary EPI layer and a self-aligned technique, and to reduce the size, which is suitable for ultra-high-speed integrated circuits. It is to provide a method for manufacturing a transistor.
이하 본 발명에 의한 NPN형 트랜지스터의 제조방법을 첨부도면에 도시한 실시예에 따라서 상세히 설명한다.Hereinafter, a method of manufacturing an NPN transistor according to the present invention will be described in detail according to the embodiment shown in the accompanying drawings.
제2도는 본 발명에 의한 NPN형 트랜지스터의 제조공정을 도시하는 것이다.2 shows the manufacturing process of the NPN transistor according to the present invention.
[제1공정] 산화처리공정[Step 1] Oxidation Treatment Process
제2(a)도와 같은 P형 기판(1)위에 선택적인 산화처리를 실시하여 SiO2층(2)을 형성한다.Selective oxidation treatment is performed on the P-type substrate 1 as shown in FIG. 2 (a) to form the SiO 2 layer 2.
[제2공정] P-EPI층 성장공정[Step 2] P-EPI Layer Growth Process
제2(b)와 같이 P-EPI층(3)을 성장시킨다. 이 공정에서 P-EPI층(3)을 성장시키면 SiO2층(2) 영역이 성장하게 되어 후에 절연영역으로 사용된다.As in the second (b), the P-EPI layer 3 is grown. In this process, when the P-EPI layer 3 is grown, the SiO 2 layer 2 is grown, which is then used as an insulating region.
[제3공정] 실리콘 에치 공정[Step 3] Silicon Etching Process
상기 제2공정에서의 P-EPI층(3)에 제2(c)도와 같이 실리콘 에치를 실시한다. 여기서 P-EPI층(3)에 그루브(4)가 형성되며, 양측의 P-POLY층(5)의 일부가 노출된다.Silicon etch is performed on the P-EPI layer 3 in the second step as shown in FIG. The groove 4 is formed in the P-EPI layer 3, and a part of the P-POLY layer 5 on both sides is exposed.
[제4공정] 서멀 산화처리 공정[Step 4] Thermal Oxidation Process
제2(d)와 같이, 서멀 산화처리(THERMAL OXIDATION)하여 상기 P-EPI층(3)과 P-POLY층(5) 상에 SiO2층(2)을 형성한다.As in the second (d), the thermal oxidation treatment (THERMAL OXIDATION) to form a SiO 2 layer 2 on the P-EPI layer 3 and the P-POLY layer (5).
[제5공정] 활성영역 개방 및 N+이식공정[Step 5] Active Area Opening and N + Implantation Process
제2(e)도와 같이, 활성영역(6)을 개방하여 N+를 이식한다.As shown in FIG. 2 (e), the active region 6 is opened to implant N + .
[제6공정] 2차 EPI층 형성공정[Step 6] Second EPI Layer Formation Process
제2(f)와 같이, 활성영역(6)에 버리드층(7)을 형성하고 그 위에 2차 EPI층(7')을 형성한 다음 애닐링처리하여 재결정화를 실시한다.As in the second (f), the buried layer 7 is formed in the active region 6, the secondary EPI layer 7 'is formed thereon, and then annealing is performed to recrystallize.
[제7공정] 산화막처리 및 P+이식공정[Step 7] Oxide Treatment and P + Transplantation Process
제2(g)와 같이, SiO2층(2)과 2차 EPI층(7')위에 산화막(8)을 형성하고, 그 위에 P+를 이식하여 도핑된 폴리층(9)을 형성한다. 이때 베이스영역이 정의된다.As in the second (g), an oxide film 8 is formed on the SiO 2 layer 2 and the secondary EPI layer 7 ', and P + is implanted thereon to form a doped poly layer 9. At this time, the base area is defined.
[제8공정] 베이스단자부 에치공정[Step 8] Base Terminal Part Etching Step
제2(h)와 같이, 도핑된 폴리층(9)에서 베이스단자로 사용할 부분을 에치한다.As in the second (h), the portion to be used as the base terminal in the doped poly layer 9 is etched.
[제9공정] N+이식공정[Step 9] N + Implantation Process
제2(i)와 같이, N+를 이식하여 에미터 및 콜렉터 영역을 형성한다.As in second (i), N + is implanted to form emitter and collector regions.
[제10공정] 단자형성공정[Step 10] Terminal Formation Process
제2(j)와 같이, 각 단자(B)(E)(C)을 형성하고 보호층(10)을 형성하여 완성된 제품을 얻는다.As in the second (j), each terminal (B) (E) (C) is formed and the protective layer 10 is formed to obtain a finished product.
이상과 같이 본 발명에 의하면 폴리를 이용하여 절연영역을 정의함으로써 공정진행시 절연공정에서 생기는 사이드 디퓨션 및 소스에 의한 표면오염을 방지할 수 있으며, 공정이 간단하고, 크기를 최소화할 수 있어 웨이퍼의 손실을 줄일 수 있게 되는 것이다.As described above, according to the present invention, by defining an insulation region using poly, it is possible to prevent surface contamination caused by side diffusion and source generated during the insulation process during the process, and to simplify the process and minimize the size of the wafer. The loss of will be reduced.
또한 패러스틱 캐패시탠스(PARASTIC CAPACITANCE) 및 RCS등을 중일으로써 주파수 특성이 양호하게 되는 것이다.In addition, the frequency characteristics are improved by using the PARASTIC CAPACITANCE and the RCS.
따라서 본 발명에 의하면 폴리를 이용하여 절연층을 형성하고 2차 EPI층과 셀프얼라인 기법을 이용하여 오버 에치나 확산시 오염을 방지하고 크기를 소형화할 수 있어 초고속 집적회로의 제조에 적합한 것이다.Therefore, according to the present invention, the insulating layer is formed using poly, and the secondary EPI layer and the self-aligned technique can be used to prevent contamination during over-etching and diffusion and to reduce the size, which is suitable for manufacturing high-speed integrated circuits.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019713A KR930004298B1 (en) | 1990-12-01 | 1990-12-01 | Making method of npn type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019713A KR930004298B1 (en) | 1990-12-01 | 1990-12-01 | Making method of npn type transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920013741A KR920013741A (en) | 1992-07-29 |
| KR930004298B1 true KR930004298B1 (en) | 1993-05-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900019713A KR930004298B1 (en) | 1990-12-01 | 1990-12-01 | Making method of npn type transistor |
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| Country | Link |
|---|---|
| KR (1) | KR930004298B1 (en) |
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1990
- 1990-12-01 KR KR1019900019713A patent/KR930004298B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920013741A (en) | 1992-07-29 |
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