JPS5832464A - Vertical type tetrode mosfet - Google Patents
Vertical type tetrode mosfetInfo
- Publication number
- JPS5832464A JPS5832464A JP56130554A JP13055481A JPS5832464A JP S5832464 A JPS5832464 A JP S5832464A JP 56130554 A JP56130554 A JP 56130554A JP 13055481 A JP13055481 A JP 13055481A JP S5832464 A JPS5832464 A JP S5832464A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- mosfet
- layers
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 210000000576 arachnoid Anatomy 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
Description
【発明の詳細な説明】
本発明は２個のゲートをもつ４極Ｍ０８ＦＥＴに関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a quadrupole M08FET with two gates.
４極Ｍ０８Ｆ’ＥＴは、第１図の回路図に示すように、
Ｇ１およびＧ箕の２個のゲートをもっＦＥＴである。The 4-pole M08F'ET, as shown in the circuit diagram in Figure 1,
It is an FET with two gates, G1 and G-win.
第２図は、このような４極Ｍ０８ＦＥＴのうち、従来の
横型の４極ＭＯ８ＦＥＴの断面図を示す。第２図におい
そ、１１はＰ型基板、１２はＰ型基板１１に形成された
ドレイン部Ｎ＋層、１２ａはドレイン部の隣接するＮ
層、１３はンース・ドレイン部中間のＮ 層、１４はソ
ース部のＮ＋層で１４ａは隣接Ｎ 層、１６はＮ 層１
３と１４ａとめ間の上面の絶縁［１５を介して設けられ
た第１ゲート、１７はＮ 層１３と１２ａとの間の上面
の絶縁膜１５を介して設けられた第２ゲート、１９と２
０はそれぞれドレイン部とソース部に設けられた第１主
電極と第２主電極、１８．２１は表面像膜の熱酸化膜で
ある。 ・□このような従来の４極ＭＯ８ＦＥＴに
おいては、よく知られているように、第２ゲート１７の
電圧増幅率がＫのとき、第１ゲート１６とドレイン１９
との間の帰還容量ＣＤＧＩとすると、この帰還容量はｌ
／にとなって高周波動作に適している。しかし、高圧化
、大電流化は横型のため困難である。FIG. 2 shows a cross-sectional view of a conventional horizontal 4-pole MO8FET among such 4-pole M08FETs. In FIG. 2, 11 is a P type substrate, 12 is a drain part N+ layer formed on the P type substrate 11, and 12a is an N+ layer adjacent to the drain part.
13 is the N layer between the source and drain parts, 14 is the N+ layer in the source part, 14a is the adjacent N layer, and 16 is the N layer 1.
A first gate provided via an insulating film 15 on the upper surface between 3 and 14a, 17 is a second gate provided via an insulating film 15 on the upper surface between layers 13 and 12a, and
0 is a first main electrode and a second main electrode provided in the drain section and the source section, respectively, and 18.21 is a thermal oxidation film of the surface image film.・□In such a conventional 4-pole MO8FET, as is well known, when the voltage amplification factor of the second gate 17 is K, the first gate 16 and the drain 19
CDGI, this feedback capacitance is l
/, making it suitable for high frequency operation. However, increasing the voltage and current is difficult because it is horizontal.
本発明の目的は、高周波動作に適すると共に、高耐圧で
大電流動作の可能な４極ＭＯ８ＦＥＴを提供するにある
。An object of the present invention is to provide a 4-pole MO8FET that is suitable for high frequency operation, has a high breakdown voltage, and is capable of large current operation.
本発明の４極ＭＯ８ＦＥＴは、ＰまたはＮ導電型のうち
一方の一導電型の半導体基板に反対導電型の第２層が形
成され、この反対導電型第２層内に一導電型の第３層と
第４層が形成され、前記−導電型の基板第１層と第３層
との間の反対導電型第２層上面および前記−導電型の第
３層と第４層の間の反対導電型第２層上面にそれぞれ絶
縁膜を介してゲート電極が形成され、前記反対導電型第
２層に接続して第２主電極が形成され、前記−導電型基
板第１層に接続して第１主電極が形成された構成を有す
る。In the 4-pole MO8FET of the present invention, a second layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type of P or N conductivity type, and a third layer of one conductivity type is formed in this second layer of opposite conductivity type. a second layer of opposite conductivity type between the first layer and the third layer of the substrate of conductivity type and a second layer of opposite conductivity type between the third layer and the fourth layer of said conductivity type; A gate electrode is formed on the upper surface of the second layer of conductivity type via an insulating film, a second main electrode is formed connected to the second layer of opposite conductivity type, and a second main electrode is formed connected to the first layer of the -conductivity type substrate. It has a configuration in which a first main electrode is formed.
つぎに本発明を実施例によシ説明する。Next, the present invention will be explained using examples.
第３図は本発明の一実施例の断面図である。第３図にお
いて、１はＮ−型の半導体基板のうち、後の工程で形成
された拡散層部分を含まない残りの基板第１層である。FIG. 3 is a sectional view of one embodiment of the present invention. In FIG. 3, reference numeral 1 denotes the remaining first layer of the N-type semiconductor substrate that does not include the diffusion layer portion formed in a later step.
２は基板内に複数個形成されたＰ型の第２層、３，４は
、Ｐ型第２層内に選択的に形成されたそれぞれ対をなす
Ｎ 層、６はＮ型基板第１層１とＮ型第３層３との間の
Ｐ型箱２層の上面に絶縁膜５を介して形成された第２ゲ
ート電極、７はＮ型第３層３とＮ型第４層４との間のＰ
型第２層上面に絶縁膜５を介して形成された第１ゲート
電極、１０は、第１ゲートおよび第２ゲートとは絶縁熱
酸化膜８で絶縁されて各Ｐ型箱２層に共通に接続された
第２主電極、９はＮ型基板第１層１に接続された第１主
電極である。2 is a plurality of P-type second layers formed in the substrate; 3 and 4 are paired N layers selectively formed in the P-type second layer; 6 is the N-type first layer of the substrate. A second gate electrode is formed on the upper surface of the P-type box 2 layer between 1 and the N-type third layer 3, with an insulating film 5 interposed therebetween; P between
A first gate electrode 10 formed on the upper surface of the second layer of the mold via an insulating film 5 is insulated from the first gate and the second gate by an insulating thermal oxide film 8, and is common to the two layers of each P-type box. The connected second main electrode 9 is the first main electrode connected to the first layer 1 of the N-type substrate.
このような本発明の縦型４極Ｍ０８ＦＥＴでは、第１主
電極９と第２主電極との間に印加された電源電圧に対し
、第１ゲート電極７と第２ゲート電極６の下のｎ型チャ
ンネルを通り、Ａで示す径路の電流が流れる。In such a vertical quadrupole M08FET of the present invention, the n below the first gate electrode 7 and the second gate electrode 6 with respect to the power supply voltage applied between the first main electrode 9 and the second main electrode A current flows along the path indicated by A through the mold channel.
このような構造においては、Ｎ型基板第１層１とＰ型筒
２層２との間のＰＮ接合の耐圧は、表面部の接合耐圧で
決定されない。これは隣り合ったＰ型筒２層２から延び
る空乏層が接触し、この空蓬層が基板と平行になる丸め
である。このため、高耐圧化する丸めの手段、例えばガ
ードリングを個々のＭＯ８要素部に設けることなく、こ
れら多数の要素を含むチップ外周部のみに設ければよい
ので、個々の要素に高耐圧化手段を施す九めに多くの面
積を要し九従来の横型ＭＯ８ＰＥＴに比べ、多数のＭＯ
８ＦＥＴを高密度で形成でき、同一面積のチップでは、
大幅な高耐圧大電流化が可能となる。In such a structure, the breakdown voltage of the PN junction between the N-type substrate first layer 1 and the P-type cylinder second layer 2 is not determined by the junction breakdown voltage of the surface portion. This is a round shape in which depletion layers extending from two adjacent P-type cylinder layers 2 are in contact with each other, and this depletion layer is parallel to the substrate. For this reason, it is not necessary to provide a rounding means for increasing the withstand voltage, such as a guard ring, on each MO8 element part, but only on the outer periphery of the chip that includes a large number of these elements. Compared to the conventional horizontal MO8PET, it requires a large amount of area to apply
8FETs can be formed with high density, and in a chip with the same area,
Significantly high withstand voltage and large current becomes possible.
なお、上側では一導電型をｎ型、反対導電型をＰ型に対
応させ、かつ、ＮチャンネルＭＯ８ＦＥＴについて説明
したが、上記対応を逆にしたＰチャンネルＭＯ８ＦＥＴ
についても本発明が適用されるのは自明である。In addition, in the upper part, one conductivity type corresponds to n type and the opposite conductivity type corresponds to p type, and an N-channel MO8FET was explained, but a P-channel MO8FET in which the above correspondence is reversed is explained.
It is obvious that the present invention is also applicable to.
第１図は４極Ｍ０８ＦＥＴの回路図、第２図社従来の横
型４極Ｍ０８ＦＥＴの断面図、第３図は本発明の一実施
例の断面図である。
１・・・・・・Ｎ型基板第１層、２・・・・・・Ｐ型箱
２層、３・・・・・・Ｎ型第３層、４・・・・・・Ｎ型
第４層、５・・・・・・ゲート絶縁膜、６・・・・・・
第２ゲート電極、７・・・・・・第１ゲート電極、８−
・・・・・表面保饅絶鰍膜、９−−−・・第１主電極、
１０・・・・・・第２主電極。FIG. 1 is a circuit diagram of a 4-pole M08FET, FIG. 2 is a sectional view of a conventional horizontal 4-pole M08FET, and FIG. 3 is a sectional view of an embodiment of the present invention. 1...N-type substrate first layer, 2...P-type box 2 layer, 3...N-type third layer, 4...N-type third layer 4 layers, 5...gate insulating film, 6...
Second gate electrode, 7...First gate electrode, 8-
・・・・Surface-protected arachnoid membrane, 9---・First main electrode,
10... Second main electrode.
Claims (1)
に反対導電型の第２層が形成され、この反対導電型第２
層内に一導電型の第３層と第４層が形成され、前記−導
電型の基板第１層と第３層との間の反対導電型第２層上
面および前記−導電型の第３層と第４層の間の反対導電
型第２層上面にそれぞれ絶縁膜を介してゲート電極が形
成され、前記反対導電型第２層に接続して第２主電極が
形成され、前記−導電型基板第１層に接続して第１主電
極が形成されていることを特徴とする縦型４極ＭＯ８Ｆ
ＥＴ ０A second layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type of P or N conductivity type;
A third layer and a fourth layer of one conductivity type are formed in the layer; A gate electrode is formed on the upper surface of the second layer of the opposite conductivity type between the second layer and the fourth layer via an insulating film, a second main electrode is formed connected to the second layer of the opposite conductivity type, and a second main electrode is formed connected to the second layer of the opposite conductivity type. A vertical quadrupole MO8F characterized in that a first main electrode is formed connected to the first layer of the mold substrate.
ET 0
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56130554A JPS5832464A (en) | 1981-08-20 | 1981-08-20 | Vertical type tetrode mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56130554A JPS5832464A (en) | 1981-08-20 | 1981-08-20 | Vertical type tetrode mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5832464A true JPS5832464A (en) | 1983-02-25 |
Family
ID=15037044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56130554A Pending JPS5832464A (en) | 1981-08-20 | 1981-08-20 | Vertical type tetrode mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832464A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4936359A (en) * | 1972-08-03 | 1974-04-04 | ||
| JPS544079A (en) * | 1977-06-10 | 1979-01-12 | Sony Corp | Semiconductor device |
-
1981
- 1981-08-20 JP JP56130554A patent/JPS5832464A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4936359A (en) * | 1972-08-03 | 1974-04-04 | ||
| JPS544079A (en) * | 1977-06-10 | 1979-01-12 | Sony Corp | Semiconductor device |
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