JPS5832425A - 回路素子接続方法 - Google Patents

回路素子接続方法

Info

Publication number
JPS5832425A
JPS5832425A JP56120445A JP12044581A JPS5832425A JP S5832425 A JPS5832425 A JP S5832425A JP 56120445 A JP56120445 A JP 56120445A JP 12044581 A JP12044581 A JP 12044581A JP S5832425 A JPS5832425 A JP S5832425A
Authority
JP
Japan
Prior art keywords
pellets
wiring
circuit elements
circuit element
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56120445A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6233749B2 (enExample
Inventor
Shoji Takishima
滝島　昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP56120445A priority Critical patent/JPS5832425A/ja
Priority to US06/400,815 priority patent/US4843035A/en
Publication of JPS5832425A publication Critical patent/JPS5832425A/ja
Publication of JPS6233749B2 publication Critical patent/JPS6233749B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP56120445A 1981-07-23 1981-07-31 回路素子接続方法 Granted JPS5832425A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56120445A JPS5832425A (ja) 1981-07-31 1981-07-31 回路素子接続方法
US06/400,815 US4843035A (en) 1981-07-23 1982-07-22 Method for connecting elements of a circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56120445A JPS5832425A (ja) 1981-07-31 1981-07-31 回路素子接続方法

Publications (2)

Publication Number Publication Date
JPS5832425A true JPS5832425A (ja) 1983-02-25
JPS6233749B2 JPS6233749B2 (enExample) 1987-07-22

Family

ID=14786377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56120445A Granted JPS5832425A (ja) 1981-07-23 1981-07-31 回路素子接続方法

Country Status (1)

Country Link
JP (1) JPS5832425A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4815208A (en) * 1987-05-22 1989-03-28 Texas Instruments Incorporated Method of joining substrates for planar electrical interconnections of hybrid circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4815208A (en) * 1987-05-22 1989-03-28 Texas Instruments Incorporated Method of joining substrates for planar electrical interconnections of hybrid circuits

Also Published As

Publication number Publication date
JPS6233749B2 (enExample) 1987-07-22

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