JPS5827332A - リードフレームを用いた半導体装置の製造方法 - Google Patents
リードフレームを用いた半導体装置の製造方法Info
- Publication number
- JPS5827332A JPS5827332A JP12546081A JP12546081A JPS5827332A JP S5827332 A JPS5827332 A JP S5827332A JP 12546081 A JP12546081 A JP 12546081A JP 12546081 A JP12546081 A JP 12546081A JP S5827332 A JPS5827332 A JP S5827332A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- bin
- strip
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000005452 bending Methods 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 description 10
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 230000007613 environmental effect Effects 0.000 description 2
- 238000006748 scratching Methods 0.000 description 2
- 230000002393 scratching effect Effects 0.000 description 2
- 238000010186 staining Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12546081A JPS5827332A (ja) | 1981-08-11 | 1981-08-11 | リードフレームを用いた半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12546081A JPS5827332A (ja) | 1981-08-11 | 1981-08-11 | リードフレームを用いた半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827332A true JPS5827332A (ja) | 1983-02-18 |
| JPH0131687B2 JPH0131687B2 (enrdf_load_stackoverflow) | 1989-06-27 |
Family
ID=14910636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12546081A Granted JPS5827332A (ja) | 1981-08-11 | 1981-08-11 | リードフレームを用いた半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827332A (enrdf_load_stackoverflow) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991004575A1 (en) * | 1989-09-12 | 1991-04-04 | Kabushiki Kaisha Toshiba | Lead frame for semiconductor device and semiconductor device using the lead frame |
| US5343072A (en) * | 1990-08-20 | 1994-08-30 | Rohm Co., Ltd. | Method and leadframe for making electronic components |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559749A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Lead frame |
-
1981
- 1981-08-11 JP JP12546081A patent/JPS5827332A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559749A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Lead frame |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991004575A1 (en) * | 1989-09-12 | 1991-04-04 | Kabushiki Kaisha Toshiba | Lead frame for semiconductor device and semiconductor device using the lead frame |
| US5200806A (en) * | 1989-09-12 | 1993-04-06 | Kabushiki Kaisha Toshiba | Lead frame having a plurality of island regions and a suspension pin |
| US5343072A (en) * | 1990-08-20 | 1994-08-30 | Rohm Co., Ltd. | Method and leadframe for making electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0131687B2 (enrdf_load_stackoverflow) | 1989-06-27 |
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