JPS5827332A - Lead frame and manufacture of semiconductor device employing the same - Google Patents
Lead frame and manufacture of semiconductor device employing the sameInfo
- Publication number
- JPS5827332A JPS5827332A JP12546081A JP12546081A JPS5827332A JP S5827332 A JPS5827332 A JP S5827332A JP 12546081 A JP12546081 A JP 12546081A JP 12546081 A JP12546081 A JP 12546081A JP S5827332 A JPS5827332 A JP S5827332A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- bin
- strip
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、リードフレームおよびそのリードフレームを
用いえ半導体装置の製造方法Ｃ二関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame and a method of manufacturing a semiconductor device using the lead frame.
従来の半導体装置用リードフレームの構造は第１図ζ：
示すようになっている。すなわち、平行に配設されえ連
結条帯１，１およびこれと直交して離関配設蕃れたリー
ド線連結部分２，２からなる枠部分１と、リード線連結
部分２，２と平行でかつａ結条帯１，１間Ｃ二跨設され
九メイストνツ１４と、このタイストリップ４（ニ一端
が遜結し他端が半導体チップ装着パッド５ζ＝隣接する
よう（：延在する複数の内部リードピント・・と、タイ
ストリップ４および内部リードビンＣ・・・と一端が連
結し、他端が下方のリード線連結部分Ｉと連結する複数
の外部シードビン！・・・とからなる構成（＝なってい
る。The structure of a conventional lead frame for semiconductor devices is shown in Figure 1ζ:
It is as shown. That is, there is a frame portion 1 consisting of connecting strips 1, 1 arranged in parallel and lead wire connecting portions 2, 2 disposed perpendicularly to the lead wire connecting portions 2, 2; A tie strip 4 (one end of which is connected with the other end of the semiconductor chip mounting pad 5ζ=adjacent (: a plurality of extending A configuration consisting of an internal lead pinto... and a plurality of external seed bins!... one end of which is connected to the tie strip 4 and the internal lead bin C..., and the other end of which is connected to the lower lead wire connection portion I ( = has become.
このような構造のリードフレームを用いて、図示しない
が半導体チップを装着パッドｌ（二取着し、半導体チッ
プの電極と各内部リードビン６・−・とを金属細線ζ二
よ）互いＣ二電気的接続し。Using a lead frame having such a structure, a semiconductor chip (not shown) is attached to mounting pads L (2), and the electrodes of the semiconductor chip and each internal lead bin 6 are connected to thin metal wires ζ2 and C2 electrically to each other. connection.
そして２点鎖線で示す部分を樹脂外！！器でモールドし
喪後、枠部分Ｊシよびタイストリップ４を各９−ドピン
から切断するカッティング工程。And the part indicated by the two-dot chain line is outside the resin! ! After molding with a container and cutting, the frame portion J and tie strip 4 are cut from each 9-doped pin.
および各外部リードピント・・のベンディンダニ１Ｍに
よ）、１個１個の半導体装置１ごとＣ：切〉離され、そ
れぞれ独立し良状態（二おかれる。このようｃ：１個１
個の状態にしたのち、固定支持装置中！ガジンなど６二
再度セットして、１ｉＰｒｓデイツグエ寝中電気的特性
試験、寿命試験、環境試験などを行っていた。このため
手間と時間が掛か）、生産の能率アップ中生産向上の画
から電量的でない欠点があった。さらに、これら工程が
作業者（二よる手作業である丸め、作業時にリードビン
の曲シ、ねじれ、モールド樹脂の汚れ、傷、欠けなどの
外観上の問題も発生するなどの欠点があった。and each external lead focus (by the bending mite 1M), each semiconductor device 1 is separated, and each is placed independently in good condition.
After making it into a single state, it is in a fixed support device! I re-set the 62 gauges, etc., and conducted electrical characteristics tests, life tests, environmental tests, etc. while the 1iPrs was sleeping. For this reason, it took time and effort), and had the disadvantage that the amount of electricity was not sufficient to improve production efficiency. In addition, these processes have disadvantages such as rounding, which is manual work by the operator, and appearance problems such as bending and twisting of the lead bin, staining, scratching, and chipping of the molding resin.
本発明は上記事情Ｃ：鑑みてなされ丸もので、その目的
とするところは、枠部分に固定されるダミーリードビン
を設は為こと（二よって、半導体装置の製造（ニおける
手作業工程を減少させ。The present invention has been made in view of the above-mentioned situation C, and its purpose is to provide a dummy lead bin that is fixed to the frame (2). Reduce.
半導体装置の生産性を著しく向上し得るリードフレーム
を提供すること１二ある。It is an object of the present invention to provide a lead frame that can significantly improve the productivity of semiconductor devices.
また、本発明は、リードフレームに半導体チップを装着
し、かり樹脂外囲器をモールドし九後、ダζ−リードビ
ンを除く他のリードビンを枠部分から切）離し、ダミー
リードビンのみＣ：よってモールドし大半導体チップを
支持し喪状態で、モールドし大半導体チップを所望の方
向に曲けること４二よル、リードビンを枠部分６二よっ
て形成される面外Ｃ二向けて半田デイツプ工程を行うよ
う（＝し九餉記リードフレームを用いた率導体装置の製
造方法を提供することを目的とする。In addition, in the present invention, after mounting a semiconductor chip on a lead frame and molding a resin envelope, the other lead bins except the lead bin are separated from the frame part, and only the dummy lead bin C is removed. Supporting the molded large semiconductor chip and bending the molded large semiconductor chip in a desired direction 42, the solder dip process is performed with the lead bin facing the out-of-plane C2 formed by the frame portion 62. The purpose of the present invention is to provide a method for manufacturing a conductor device using a lead frame.
以下、本発明の一実施例（二ついて図面を参照して説明
する。なお、第１図と同一部分（＝は同一符号を付して
説明する。第２図（二おいて、長手方向ζ二平行（＝配
設された連結条帯１．′ＩＩ：対し直角にリード線遅結
部分２，２を互い６二離聞配置して連結条帯１，１と連
結させ、これら−二よって複数の半導体チップの枠部分
Ｊを設ける。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.The same parts as in FIG. Two parallel (= arranged connecting strips 1.'II: The lead wire late connecting portions 2, 2 are arranged at right angles to the connecting strips 1, 2, and are connected to the connecting strips 1, 1 by 62 distances from each other. A frame portion J for a plurality of semiconductor chips is provided.
なお、第２図は１個の半導体チップの部分だけを拡大し
て示しである。すなわち％連結条帯１．１関Ｃ二これと
直交してリード線這結部２，２を互いに平行離間して設
け、かつ連結条帯１゜１と一体化し、これらＣ二よって
枠部分１を構成し、さらＣニタイストリップ４をリード
線這結部分２．２間ζ二それらと平行Ｃ二股けて連結条
帯１．１間に跨設し、タイストリップ４と一方（上方）
のリード線連結部分２との閲６二、一端がタイストリッ
プ４と連結され、他端が半導体チップ装着パッド５（＝
隣接して延在する複数の内部リードビン６・・・を設け
る。また、タイストリップ４と他方（下方）のリード線
遅結一部分２との間Ｃ二、一端が内部リードビン６・・
・およびタイストリップ４と連結し、他端が他方（下方
）のリード線連結部分２と連結する複数の外部リードビ
ンｒ・・・が設けられ九構成Ｃ：、なっている。Note that FIG. 2 shows only one semiconductor chip in an enlarged manner. That is, the lead wire connecting portions 2, 2 are provided parallel to and spaced from each other perpendicularly to the connecting strip 1.1 and C2, and are integrated with the connecting strip 1.1, and these C2 form the frame portion 1. In addition, the C tie strip 4 is placed between the lead wire connecting portions 2.2 and ζ2 parallel to them and straddled between the connecting strips 1.1, and the tie strip 4 and one (upper)
62, one end is connected to the tie strip 4, and the other end is connected to the semiconductor chip mounting pad 5 (=
A plurality of internal lead bins 6 extending adjacent to each other are provided. Also, between the tie strip 4 and the other (lower) lead wire slow connection part 2, one end is connected to the internal lead bin 6.
and a plurality of external lead bins r connected to the tie strips 4 and having the other end connected to the other (lower) lead wire connecting portion 2.
このような構造のり−ドッレームは紡速したように周知
であるが１本発明では更６二枠部分３（二固定されるダ
ミーリードビン９．夕を有スルことである。すなわち、
たとえば一方（上方）のリード線連結部分２とタイスト
リップ４七の間で、かつ相対向する連結条帯２，２の各
内側６；ダに一リードピンク、＃がそれぞれ設けられゐ
ヵこのダミーリードビン９．＃の長さは、少なくともモ
ールド工程時に半導体チップの樹脂外囲器内砿：先端部
が埋込固定宴れゐ長さが必要である。Although such a structure is well known, the present invention further includes a dummy lead bin 9, which is fixed to the frame portion 3.
For example, between one (upper) lead wire connecting portion 2 and the tie strip 47, and on each inner side 6 of the opposing connecting strips 2, 2, a lead pink and # are provided respectively on this dummy. Lead bin9. The length # must be at least long enough to allow the tip to be embedded and fixed within the resin envelope of the semiconductor chip during the molding process.
このようＣ二構成され九リードフレームの装着パッド５
舊：半導体チップ（図示しない）を数階し、半導体チッ
プの電極と各内部リードビンｄ・−とを互いに金属細線
で電気的接続し、しかる後モールドエ１１ｒ−よ〕２点
鎖線で示す部分を樹脂外囲器（図示しない）でモールド
して、半導体ＩＮｔｌを構成する。このとき、上記樹脂
外囲器Ｃニダンーリードピン９．１がそれぞれ埋設支持
される。このようにして、樹脂外囲器をモールド形成し
た後、タイストリップ４を各内部リードビンｌ−から、
ｔたリード線連結部分２゜２を各外部リードピント・・
からそれぞれ切断分離を行う（カッティング工程）、こ
のカッティングエｌＩｒ−よ）、モールＶされた各半導
体チップ、りｔ）半導体装置Ｂはダイ−リードビン９、
ｌのみによって枠部分Ｊ（＝支持され為ことになる。こ
の状態で半導体装置８を、ダミーリードビン９．＃を支
点として機械的強度を考慮しながら枠部分Ｉの平面に対
して曲げる。たとえばＩＥ３図に示すように垂直方向Ｃ
：曲げる（ベンディンダニ寝）、このベンディング工程
が終了すると、第３Ｈのように多数の半導体装置８・・
・が枠部分１ｒ：、支持専れ良状態（：なる、この状態
で、多数の半導体装置８・・・（二対して同時（二半田
デイプ工程を容易に行うことができる。このようにして
半田付は工程を終了した後、多数の半導体装ｔ８・・・
を同時（＝試験装置６ニセツトして電気的特性を測定す
ることができる。を九、寿命試験中環境試験も同時（＝
行うことができる。このよう（＝、第３図の状態で半田
ディツプや試験の工程を実施できるので、これらの工程
を行うに轟っては、外部リードピント・・の変形や半導
体装置８のモールド樹脂の汚れ、傷、欠けなどの心配を
する必要がなく、スムーズ４二半田デイツプや性能およ
び信頼性の試験を行うことができる。このようＣ二°し
て試験工程か終了した後、ダイ−リードビン９，９の部
分で切断してそれぞれ独立した半導体装置８を得ること
かできる。In this way, C2 is configured with nine lead frame mounting pads 5
舊：Semiconductor chip (not shown) is mounted several times, the electrodes of the semiconductor chip and each internal lead bin d and - are electrically connected to each other with thin metal wires, and then molded to molder 11r] The part shown by the two-dot chain line is molded with resin. The semiconductor INtl is formed by molding with an envelope (not shown). At this time, the lead pins 9.1 of the resin envelope C are embedded and supported, respectively. After molding the resin envelope in this way, tie strips 4 are inserted from each internal lead bin l-.
Attach the lead wire connection part 2゜2 to each external lead focus...
The semiconductor device B is cut and separated from each other (cutting process).
The semiconductor device 8 is now supported by the frame portion J only by the frame portion I. In this state, the semiconductor device 8 is bent with respect to the plane of the frame portion I using the dummy lead bin 9.# as a fulcrum while considering mechanical strength. For example, Vertical direction C as shown in IE3 diagram
: Bending (bending). When this bending process is completed, a large number of semiconductor devices 8 as shown in 3H...
・The frame portion 1r: is fully supported (: In this state, a large number of semiconductor devices 8... (two solder dip processes can be easily performed for two at the same time.) After completing the soldering process, a large number of semiconductor devices t8...
Simultaneously (= test equipment 6 can be set up to measure the electrical characteristics. 9. Environmental tests can also be performed simultaneously during the life test (=
It can be carried out. Since the solder dipping and testing processes can be carried out in the state shown in Figure 3, these processes will prevent deformation of the external lead focus, dirt on the mold resin of the semiconductor device 8, etc. You can perform smooth solder dips, performance and reliability tests without having to worry about scratches, chips, etc.After the test process is completed by heating the die-lead bins 9 and 9, It is possible to obtain independent semiconductor devices 8 by cutting at the portions shown in FIG.
なお、ダミーリードビン９．９は、たとえば！Ｐ：４図
６＝示りように近接する内部リードビン６、ｇｔニ一体
６二接続する構造でもよい、また、前記実施例では、ダ
ミーリードビンを２ケ所設は九場合ζ二ついて説明した
か、２ヶ所Ｃ二限らす３ケ所でも４ケ所でもよく、所望
すゐ強贋に応じて選択することかできる。In addition, the dummy lead bin 9.9 is for example! P: 4 As shown in Fig. 6, it is also possible to have a structure in which two adjacent internal lead bins 6 are connected to one another.Also, in the above embodiment, two dummy lead bins are installed in nine cases. , there may be two locations, but there may be three or four locations, which can be selected depending on the desired authenticity.
以上詳述したようＣ二本発明ζ：よれば、枠部分に固定
されるダミーリードピンを有するリードフレームを用い
ることによル、カッティングあるいはカッティングーペ
ンディング工程彼の半田ディツプや電気特性、寿命およ
び環境試験などを容易区二行わしめることができ、作業
性が著しく向上する。特６二、半田デイツプ工程６＝お
いては多大の効果を奏する。しかも、リードビンの変形
やモールド樹脂の汚れ、キズ、欠けなどを生じさせるこ
となく生産性の向上を図ることかできる。As described in detail above, according to the present invention, the cutting or cutting-pending process is achieved by using a lead frame with dummy lead pins fixed to the frame part, its solder dip, electrical characteristics, lifespan and environment. Tests, etc. can be easily carried out, and work efficiency is significantly improved. Particularly 62, the solder dip step 6 has great effects. Furthermore, productivity can be improved without causing deformation of the lead bin or staining, scratching, or chipping of the mold resin.
第１図は従来の半導体装置用リードフレームの構成図、
第２図は本発明の一実施例を説明する九めのリードフレ
ームの構成図、！３図は同実施例のペンディング工程後
の構造説明図、籐４図は本発明の他の実施例を説明する
ためのリードフレームの構成図である。
・ｆ・−・連結条帯、２・・・リード線連結部分、３・
・・枠部分、４・・・タイストリップ、５・・・半導体
チップ装着パッド、６・・・内部リードビン、７・・・
外部リードビン％ ８・・・半導体装置、９・・・ダミ
ーリードビン。Figure 1 is a configuration diagram of a conventional lead frame for semiconductor devices.
FIG. 2 is a configuration diagram of the ninth lead frame explaining one embodiment of the present invention. 3 is a structural explanatory diagram of the same embodiment after the pending process, and FIG. 4 is a structural diagram of a lead frame for explaining another embodiment of the present invention.・f・-・Connection strip, 2...Lead wire connection part, 3・
... Frame portion, 4... Tie strip, 5... Semiconductor chip mounting pad, 6... Internal lead bin, 7...
External lead bin% 8...Semiconductor device, 9...Dummy lead bin.
Claims (1)
部分と、前記リード線運結部分と平行でかつ前記運結条
帯関（＝跨設され九メイストリップと、このタイストリ
ップ≦ニ一端が這結し他端か半導体チップ装着パッドー
二隣接するようζ二延在する複数の内部リードビンと、
前記り紬すｂ複数の外部リードビンと、＃記タイストリ
ップと内部リードピンの先端部との間檻二位置する前記
連結条帯の内側−一端が這結し他端が＃釦枠部分内方（
二嬌長妄れたダイ−リードビンとを臭備し九ことを特徴
とすゐリードフレーム。 （り ダイ−リードビンは内部リードピンの一部に一体
的ｒ−接続されていることを特徴とする特許請求の範囲
第１項記載のり−ド７レーム。 （３１連結条帯およびリード線遍結部分よシなる枠部分
と、前記リード線運結部分と平行でかつ前記連結条帯間
ζ二跨設され九タイストνフッと、このタイストリップ
に一端が運結し他端が半導体チップ装着パッド（＝隣接
するようｔ＝に在する複数の内部リードピンと、前記り
給する複数の外部リードピンと、前記タイストリップと
内部リードピンの先端部との閾に位置する前記連結条帯
の内側６二一端が這結し他端が前記枠部分内方に延長さ
れたダミーリードビンとを具備してなるリードフレーム
を用意すゐ工程と、半導体チップを装着パッド６二取着
し、かつ半導体チップと内部ダートビンとの電気的接続
を行ったｌＩ、半導体チップおよび内部リードビン部分
を樹腫外−器″ｅ４：一ルドすゐ工程と、次Ｃニダミー
リードビンな除く他のリードビンを枠部分から切断分離
するカッティング工程と、モールドした半導体チップを
枠部分平面Ｃ二対してダミーリードビンを支点として曲
げるベンディング工程と、ダミーリードビンを介して枠
部分ζ：支持された半導体チップの外部リードビンＣ二
対する半田付は工１とを具備し九ことを特徴とするり一
ド７レームを用いた半導体装置の製造方法。(1) A frame portion including the connecting strip and the lead wire connecting portion, and a frame portion that is parallel to the lead wire connecting portion and straddles the connecting strip, and this tie strip ≦Ni. a plurality of internal lead bins having one end tied together and extending so as to be adjacent to the other end or the semiconductor chip mounting pad;
The connecting strip is located between the plurality of external lead bins, the tie strip marked with #, and the tip of the internal lead pin.
A lead frame that is characterized by nine features: a die-lead bottle with two long lengths. (31) The die lead bin is integrally connected to a part of the internal lead pin. Nine tie strips are connected to the tie strip, and one end is connected to the tie strip, and the other end is connected to the semiconductor chip mounting pad ( = a plurality of internal lead pins located at t = adjacent to each other, a plurality of external lead pins feeding the above, and an inner side 62 of the connecting strip located at the threshold between the tie strip and the tip of the internal lead pin. A step of preparing a lead frame comprising a dummy lead bin with a dummy lead bin having two ends connected to each other and the other end extending inward of the frame portion, mounting a semiconductor chip on mounting pads 62, and connecting the semiconductor chip and the inside of the lead frame. The electrical connection with the dirt bin is made, the semiconductor chip and the internal lead bin are removed from the outside of the device. a bending process of bending the molded semiconductor chip with respect to the frame portion plane C2 using the dummy lead bin as a fulcrum, and soldering the supported semiconductor chip to the external lead bin C2 of the frame portion ζ via the dummy lead bin. 1. A method for manufacturing a semiconductor device using a 7-layer frame, characterized in that the following steps are provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12546081A JPS5827332A (en) | 1981-08-11 | 1981-08-11 | Lead frame and manufacture of semiconductor device employing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12546081A JPS5827332A (en) | 1981-08-11 | 1981-08-11 | Lead frame and manufacture of semiconductor device employing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827332A true JPS5827332A (en) | 1983-02-18 |
| JPH0131687B2 JPH0131687B2 (en) | 1989-06-27 |
Family
ID=14910636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12546081A Granted JPS5827332A (en) | 1981-08-11 | 1981-08-11 | Lead frame and manufacture of semiconductor device employing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827332A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991004575A1 (en) * | 1989-09-12 | 1991-04-04 | Kabushiki Kaisha Toshiba | Lead frame for semiconductor device and semiconductor device using the lead frame |
| US5343072A (en) * | 1990-08-20 | 1994-08-30 | Rohm Co., Ltd. | Method and leadframe for making electronic components |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559749A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Lead frame |
-
1981
- 1981-08-11 JP JP12546081A patent/JPS5827332A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559749A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Lead frame |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991004575A1 (en) * | 1989-09-12 | 1991-04-04 | Kabushiki Kaisha Toshiba | Lead frame for semiconductor device and semiconductor device using the lead frame |
| US5200806A (en) * | 1989-09-12 | 1993-04-06 | Kabushiki Kaisha Toshiba | Lead frame having a plurality of island regions and a suspension pin |
| US5343072A (en) * | 1990-08-20 | 1994-08-30 | Rohm Co., Ltd. | Method and leadframe for making electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0131687B2 (en) | 1989-06-27 |
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