JPH0328826B2 - - Google Patents
Info
- Publication number
- JPH0328826B2 JPH0328826B2 JP16675681A JP16675681A JPH0328826B2 JP H0328826 B2 JPH0328826 B2 JP H0328826B2 JP 16675681 A JP16675681 A JP 16675681A JP 16675681 A JP16675681 A JP 16675681A JP H0328826 B2 JPH0328826 B2 JP H0328826B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- pair
- lead frame
- pellet
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000008188 pellet Substances 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- 229920005989 resin Polymers 0.000 description 11
- 238000000576 coating method Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は、たとえばDIP（デユアル・インラ
イン）形パツケージの半導体装置を製造する場合
に用いられる半導体装置用リードフレームに関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame for a semiconductor device used, for example, in manufacturing a semiconductor device in a DIP (dual in-line) package.
第１図は、DIP形パツケージの半導体装置を製
造する場合に用いられる、従来のリードフレーム
の構成を示す正面図である。このリードフレーム
は鉄または銅製で、厚みが0.1〜0.6mmの細長い平
坦な金属板を打抜き加工して形成するようにした
ものである。図において、１は縦枠、２は横枠で
あり、縦枠１横枠２とで囲こまれた部分に半導体
装置１個分のリードフレームが形成されるように
なつている。そしてこの１個分のリードフレーム
は、ほぼ中央部に設けられてその表面上に半導体
ICペレツトがマウントされるペレツトマウント
部３、このペレツトマウント部３を上記縦枠１と
連結してペレツトマウント部３を保持するための
連結部４、各一方先端部が上記ペレツトマウント
部３を囲むように配置形成されかつその半数毎の
他方先端部が一定間隔を保つて上記一対の各横枠
方向に配列形成される合計16本の内部リード５，
５，…、これら各内部リード５，５…それぞれの
他方先端部から連続的に延長形成されその先端部
が上記一対の各横枠２と結合された外部リード
６，６…、上記各内、外部リード５，６の位置を
固定するためにこれらのリード相互間を連結する
と共に上記縦枠１に連結するダム部７から構成さ
れている。なお、上記内部リード５，５…と外部
リード６，６…は、便宜上、図中一点鎖線を付し
て示す樹脂モールド予定領域の内部に位置するも
のを内部リード、外部に位置するものを外部リー
ドとして区別している。また第１図において縦枠
１の連結部４形成位置付近に開孔された円形の透
孔８、４個所に開孔された方形の透孔９および円
形の透孔１０は、自動製造工程においてこのリー
ドフレームをピツチ送りする、前記ペレツトマウ
ント部３上に半導体ICペレツトをマウントする、
前記ダム部７を切断、除去して各内、外部リード
５，６を分離する、等の各工程の際に、固定用の
ガイドピンが挿入あるいは送り用の爪が挿入され
るものである。 FIG. 1 is a front view showing the structure of a conventional lead frame used when manufacturing a semiconductor device in a DIP type package. This lead frame is made of iron or copper and is formed by stamping a long and thin flat metal plate with a thickness of 0.1 to 0.6 mm. In the figure, 1 is a vertical frame and 2 is a horizontal frame, and a lead frame for one semiconductor device is formed in a portion surrounded by the vertical frame 1 and the horizontal frame 2. This one lead frame is provided almost in the center and has a semiconductor on its surface.
A pellet mount part 3 on which an IC pellet is mounted, a connecting part 4 for connecting this pellet mount part 3 with the vertical frame 1 and holding the pellet mount part 3, and a tip end of each of the pellet mount parts A total of 16 internal leads 5 are arranged to surround the part 3 and are arranged in the direction of each of the pair of horizontal frames, with the other end of each half thereof maintaining a constant interval.
5, . . . , external leads 6, 6 . In order to fix the positions of the external leads 5 and 6, a dam part 7 is provided which connects these leads to each other and to the vertical frame 1. For convenience, the inner leads 5, 5... and the outer leads 6, 6... are those located inside the resin molding area shown with dashed lines in the figure, and those located outside are referred to as external leads. It is distinguished as a lead. In addition, in FIG. 1, the circular through hole 8 drilled near the connecting portion 4 forming position of the vertical frame 1, the square through hole 9 drilled at four locations, and the circular through hole 10 are formed in the automatic manufacturing process. Pitch feeding this lead frame, mounting a semiconductor IC pellet on the pellet mounting section 3,
During each step of cutting and removing the dam portion 7 to separate the inner and outer leads 5 and 6, a fixing guide pin or a feeding claw is inserted.
このような構成でなる従来のリードフレームを
用いて半導体装置を製造するには、まずペレツト
マウント部３の表面上に半導体ICペレツトをマ
ウントし、次にこのペレツト上の各電極と各内部
リード５，５…の先端部とをAu等からなる金属
細線を用いてボンデイング法により結線し、さら
に第１図中に一点鎖線を付した樹脂モールド予定
領域を絶縁性の樹脂を用いて樹脂モールドする。
この樹脂モールド後は、外部リード６，６…を連
結しているダム部７の切断、除去によつて内、外
部リード５，６を個々に分離し、さらに外部リー
ド６，６…を所定位置で略直角に折曲形成するこ
とによつて、第２図の側面図に示すように縦枠１
によつて保持された複数個の半導体装置を得る。
次に第２図のような状態で各外部リード６，６…
への半田被覆工程が行なわれる。半田被覆工程が
終了した後は、一対の縦枠１と連結部４との間を
切断して第３図の斜視図に示すような半導体装置
が完成する。なお、第２図、第３図中、１１は樹
脂モールド部分である。 To manufacture a semiconductor device using a conventional lead frame having such a configuration, first a semiconductor IC pellet is mounted on the surface of the pellet mount section 3, and then each electrode and each internal lead on this pellet is mounted. The tips of 5, 5... are connected by a bonding method using a thin metal wire made of Au or the like, and the region to be resin molded, indicated by a dashed line in Fig. 1, is resin molded using an insulating resin. .
After this resin molding, the inner and outer leads 5, 6 are individually separated by cutting and removing the dam part 7 that connects the outer leads 6, 6..., and then the outer leads 6, 6... are placed in a predetermined position. By bending the vertical frame 1 at a substantially right angle, as shown in the side view of FIG.
A plurality of semiconductor devices are obtained, which are held by a plurality of semiconductor devices.
Next, each external lead 6, 6...
A solder coating process is performed. After the solder coating step is completed, the space between the pair of vertical frames 1 and the connecting portion 4 is cut to complete a semiconductor device as shown in the perspective view of FIG. 3. In addition, 11 in FIG. 2 and FIG. 3 is a resin molded part.
ところで、上記従来のリードフレームを用いて
半導体装置を製造する場合、前記第２図に示すよ
うな状態で外部リード６への半田被覆を行なう際
に、外部リード６に均一に半田被覆を行なうに
は、縦枠１のところまでを半田槽に浸す必要があ
る。ところが、このとき、縦枠１にも半田が付着
してこの分だけ半田が無駄になり、この結果、従
来のリードフレームを用いると半導体装置の製造
コストが高価となる欠点がある。 By the way, when manufacturing a semiconductor device using the above conventional lead frame, when coating the external leads 6 with solder in the state shown in FIG. 2, it is difficult to uniformly coat the external leads 6 with solder. , it is necessary to immerse up to the vertical frame 1 in the solder bath. However, at this time, the solder also adheres to the vertical frame 1, resulting in wasted solder.As a result, if a conventional lead frame is used, the manufacturing cost of the semiconductor device increases.
この発明は上記のような事情を考慮してなされ
たものであり、その目的とするところは、半導体
装置の製造コストを安価とすることができる半導
体装置用リードフレームを提供することにある。 The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a lead frame for a semiconductor device that can reduce the manufacturing cost of the semiconductor device.
以下図面を参照してこの発明の一実施例を説明
する。第４図はこの発明に係る半導体装置用リー
ドフレームを、従来と同様にDIP形パツケージの
ものに実施した場合の構成を示す正面図であり、
この実施例のものが従来のものと異なつている点
は、ペレツトマウント部３を縦枠１に連結する連
結部４の端部を、図中左右に位置する一対の各縦
枠１内に入り込むように延長形成するようにした
ものである。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a front view showing the structure of the lead frame for a semiconductor device according to the present invention when it is implemented in a DIP type package like the conventional one.
The difference between this embodiment and the conventional one is that the end of the connecting part 4 that connects the pellet mount part 3 to the vertical frame 1 is placed inside each of the pair of vertical frames 1 located on the left and right in the figure. It is formed so as to extend so as to fit in.
このような構成とすることにより、第４図中に
一点鎖点を付した樹脂モールド予定領域をモール
ドした後は、このモールド部分から上記連結部４
の一部が露出した状態となる。したがつて、この
モールド後に外部リード６，６…を連結している
ダム部７を切断、除去し、さらに外部リード６，
６…を折曲形成し、次に連結部４と縦枠１とが連
結された状態で縦枠１を保持してモールド部分の
上から押圧すると、上記露出している部分の連結
部４がわずかに伸びて、前記第２図に示す場合よ
りも樹脂モールド部分１１が縦枠１に対してより
下側に位置した状態の、第５図に示すような複数
個の半導体装置を得る。そして次に外部リード
６，６…への半田被覆工程が行なわれるわけであ
るが、第５図に示すように縦枠１に対して外部リ
ード６，６…はより下側に位置しているため、均
一に半田被覆を行なうには従来のように縦枠１の
ところまでを半田槽に浸す必要はない。したがつ
て縦枠１に半田が付着せず、無駄に半田を消費す
ることがなく、半導体装置の製造コストを安価と
することができる。 With such a configuration, after molding the resin mold area marked with a chain dot in FIG.
A part of it will be exposed. Therefore, after this molding, the dam part 7 connecting the external leads 6, 6... is cut and removed, and the external leads 6, 6... are cut and removed.
6 is bent and formed, and then when the vertical frame 1 is held in a state where the connecting portion 4 and the vertical frame 1 are connected and pressed from above the molded portion, the exposed portion of the connecting portion 4 is A plurality of semiconductor devices as shown in FIG. 5 are obtained in which the resin molded portion 11 is slightly elongated and positioned lower than the vertical frame 1 than in the case shown in FIG. 2. Next, the solder coating process is performed on the external leads 6, 6..., but as shown in Fig. 5, the external leads 6, 6... are located lower than the vertical frame 1. Therefore, in order to uniformly coat the solder, it is not necessary to immerse up to the vertical frame 1 in the solder bath as in the conventional case. Therefore, no solder adheres to the vertical frame 1, no solder is wasted, and the manufacturing cost of the semiconductor device can be reduced.
なお、この発明は上記一実施例に限定されるも
のではなく、たとえばこの発明をDIP形パツケー
ジを用いる半導体装置のリードフレームに実施し
たが、種々のリードフレームに実施可能であるこ
とはいうまでもない。 Note that the present invention is not limited to the one embodiment described above; for example, although the present invention was applied to a lead frame of a semiconductor device using a DIP type package, it goes without saying that it can be applied to various lead frames. do not have.
以上説明したようにこの発明によれば、連結部
の端部が一対の各縦枠内に入り込むように延長形
成して、樹脂モールドの際に上記連結部の一部が
樹脂モールド部分から露出するようにしたので、
外部リードへの半田被覆工程の際に無駄な半田を
消費せず、半導体装置の製造コストを安価とする
ことができる半導体装置用リードフレームを提供
することができる。 As explained above, according to the present invention, the end portions of the connecting portions are formed to extend into the respective vertical frames of the pair, so that a portion of the connecting portions is exposed from the resin molded portion during resin molding. I did it like this,
It is possible to provide a lead frame for a semiconductor device that does not waste solder during the process of coating external leads with solder and can reduce the manufacturing cost of the semiconductor device.
第１図は従来のリードフレームの構成を示す正
面図、第２図は上記従来のリードフレームを用い
て半導体装置を製造する際の途中工程における側
面図、第３図は完成された半導体装置の斜視図、
第４図はこの発明の一実施例に係る半導体装置用
リードフレームの構成を示す正面図、第５図は上
記実施例のリードフレームを用いて半導体装置を
製造する際の途中工程における側面図である。
１……縦枠、２……横枠、３……ペレツトマウ
ント部、４……連結部、５……内部リード、６…
…外部リード、７……ダム部、８，９，１０……
透孔、１１……樹脂モールド部分。
FIG. 1 is a front view showing the structure of a conventional lead frame, FIG. 2 is a side view of an intermediate step in manufacturing a semiconductor device using the conventional lead frame, and FIG. 3 is a diagram of a completed semiconductor device. Perspective view,
FIG. 4 is a front view showing the structure of a lead frame for a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a side view showing an intermediate step in manufacturing a semiconductor device using the lead frame of the above embodiment. be. 1... Vertical frame, 2... Horizontal frame, 3... Pellet mount section, 4... Connecting section, 5... Internal lead, 6...
...External lead, 7...Dam section, 8, 9, 10...
Through hole, 11...resin mold part.
Claims (1)
の縦枠相互間に設けられ表面上に半導体ペレツト
が載置されるペレツト載置部、このペレツト載置
部を上記一対の各縦枠に連結する一対の連結部を
備え、ペレツトが載置される上記ペレツト載置部
と共に上記一対の連結部が樹脂モールドされる半
導体装置用リードフレームにおいて、 上記一対の連結部の各端部が上記一対の各縦枠
に入り込むように延長形成されてなることを特徴
とする半導体装置用リードフレーム。[Scope of Claims] 1. A pair of vertical frames extending parallel to each other, a pellet mounting section provided between the pair of vertical frames and on which semiconductor pellets are placed, and this pellet mounting section being connected to the above-mentioned pair of vertical frames. A lead frame for a semiconductor device comprising a pair of connecting parts connected to each of the vertical frames, and in which the pair of connecting parts are resin-molded together with the pellet placing part on which pellets are placed, each of the pair of connecting parts A lead frame for a semiconductor device, characterized in that the end portions are extended so as to fit into each of the pair of vertical frames.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16675681A JPS5867054A (en) | 1981-10-19 | 1981-10-19 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16675681A JPS5867054A (en) | 1981-10-19 | 1981-10-19 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5867054A JPS5867054A (en) | 1983-04-21 |
| JPH0328826B2 true JPH0328826B2 (en) | 1991-04-22 |
Family
ID=15837141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16675681A Granted JPS5867054A (en) | 1981-10-19 | 1981-10-19 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5867054A (en) |
-
1981
- 1981-10-19 JP JP16675681A patent/JPS5867054A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5867054A (en) | 1983-04-21 |
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