JPS5826399A - Memory controller - Google Patents

Abstract

PURPOSE:To effectively execute the processing such as memory protection commonly used for a plurality of CPUs, by performing the setting of the CPUs being the objectie of memory protection with switches. CONSTITUTION:When switches 12 is entirely closed, a write signal is given to a memory device 1 via a line 17 from a protetion device 2 and datas outputted on a bus 4 are written in a specified address of the memory 1 designated with a bus 3. When an input to a terminal of an OR gate 15 goes to high level with the switch 12, the write signal given to a control terminal 11 from a CPU7 is restricted at the gate 15 and not transmitted to the line 17. As to the data of the memory 1, CPUs 5 and 6 can freely read and write, and a CPU7 can only read and the memory 1 can be protected to the CPU7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control device, and particularly to a memory control device that controls a plurality of CPUs (
The present invention relates to a memory control device suitable for arbitrarily protecting (writing prohibited) memory accessed by a central processing unit.

Conventionally, when a common memory is accessed in a system having a plurality of CPUs, a bus arbiter is used to control so that one or more CPUs do not access the same memory block at the same time.

On the other hand, in a memory device such as a RAM (Random Access Memory), a protect switch or the like is provided to prevent writing from the CPU in order to prevent and protect the stored contents from being accidentally erased. This protection function is for CPU7
Although this method is very effective in a system with a plurality of CPUs, there are disadvantages when it is used in a system with a plurality of CPUs. In other words, in such a system, due to its configuration, it may be necessary to allow writing from one CPU but prohibit writing from another CPU, so conventional memory protection methods are not used. I won't be able to do it.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory control device that can effectively carry out processing such as memory protection of a memory shared by a plurality of CPUs.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory control device according to an embodiment of the present invention, in which l represents a memory device and j represents a memory control device.

6. Three CPUs share the memory device l.

3 is an address bus that specifies the address of the memory device/;
l is a data bus for data transfer, g, de, 10
is a bus arbiter that determines permission or prohibition of the use of the address bus 3 and data bus da of the three CPUs A and '7, ko is a protect device that operates the write command terminal to the memory device/, l/ is cpUj, A, This is a control line for control signals given from 7 to the protection device 7.

FIG. 1 is a block diagram showing details of the protection device shown in FIG. 1, in which / is a switch for specifying memory protection; /3. /4I, /j' is CPU &,
A.

an OR gate for calculating the AND of the low active signal applied from the control line /l and the low active signal applied from the switch /6;
is an AND gate that takes the logical sum of the low active signals from each OR gate and sends a low active write command signal, that is, a write signal, to the memory device l via the signal line /.

Next, a case will be described in which the operation of such a configuration is performed by inhibiting a write signal to the memory element to protect the memory.

3 CPUs! ;, A, 7 are bus arbiters g, ?, which are provided correspondingly. , /θ address bus 3,
You can monopolize the data bus.

On the other hand, each CPU&, 6. ? When accessing memory device 1, first sends address data to address bus 3. On the other hand, the memory device decodes the address data and provides a chip select signal to the corresponding memory element. Next, when writing data to the memory device /, write data is sent to the data bus da, and a low active write signal is sent to the control line /l. Therefore, if the switches /, 2 are all closed, the write signal will be sent to the protect device 1t,
2 to the memory device l via the signal line 17 and output onto the data bus terminal, the data is written to a predetermined address of the memory device l specified by the memory bus 3.

On the other hand, the l of the OR gate /j is set by the switch /J.
Suppose that the terminal input is set to high level. As a result, C.P.
The write signal sent from U7 to the control terminal /l is regulated by the OR gate 13 and is not output to the signal line 17. On the other hand, CPU, the write signal sent from B to control terminal // is OR gate /J, /
Since it is not regulated by 4I, it is applied from signal line /7 to memory device /. In other words, the CPU 7 designated by the switch / is prohibited (protected) from writing data to the memory device /, and only write signals from the other CPUs A are permitted.

Therefore, the CPU, and CPUr can freely read and write data in the memory group e/, but the CPU can only read and cannot write, and in effect, the memory device/ ? It will be protected against. Of course, by changing the conditions of switch 7.2, you can freely set which CPUs to protect, and by opening all switches 7.2, you can protect the memory device for all CPUs. On the other hand, by closing all switches /L2, CPU4. A. All protection against ri will be cancelled.

In addition, in the above embodiment, the case where the setting of the CPU that is the target of memory protection is performed using a switch was exemplified.
It may also be configured such that memory protection is automatically set and canceled or a CPU to be protected is selected by software of a parent CPU provided elsewhere.

On the other hand, in the above-described embodiment, the memory protection of a memory device was described as an example, but a similar structure may be used for memory inhibiting, that is, for inhibiting both writing and reading.

As described above, according to the present invention, memory protection, which was conventionally set for each memory device or address, can be changed to CP.
It can be set for each U, and data can be handled with priority by multiple CPUs, so in the unlikely event that one CPU goes out of control 1, 7 and accidentally destroys another CPU's program 1.
Even if such operations are performed, it is possible to obtain a memory control device that can prevent this by prohibiting writing to the memory group.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control device according to an embodiment of the present invention, and FIG. 1 is a block diagram showing details of the protection device of FIG. 1. l...memory device, co...protection device, 3...
・Address bus, G...Data bus, y, A, ?・・・
・CPU. ','e /(7...bus arbiter, //...control line, /co...switch. Applicant's agent Kiyoshi Inomata (7) 653-- L, ------11- −，−yo

Claims (1)

[Claims] A memory device connected to a plurality of CPHs via an address bus and a data bus, a control line that sends a control signal from each CPU to instruct writing or reading to the memory device, and a control signal that selectively applies the control signal to the memory device. 1. A memory control device comprising: selection means connected to a control line.