JPS58223916A - ３値レベルクロツク発生回路 - Google Patents

３値レベルクロツク発生回路

Info

Publication number
JPS58223916A
JPS58223916A JP57107815A JP10781582A JPS58223916A JP S58223916 A JPS58223916 A JP S58223916A JP 57107815 A JP57107815 A JP 57107815A JP 10781582 A JP10781582 A JP 10781582A JP S58223916 A JPS58223916 A JP S58223916A
Authority
JP
Japan
Prior art keywords
voltage
power supply
output terminal
clock
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57107815A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0459807B2 (https=
Inventor
Tadahide Takada
高田　正日出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57107815A priority Critical patent/JPS58223916A/ja
Publication of JPS58223916A publication Critical patent/JPS58223916A/ja
Publication of JPH0459807B2 publication Critical patent/JPH0459807B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP57107815A 1982-06-23 1982-06-23 ３値レベルクロツク発生回路 Granted JPS58223916A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57107815A JPS58223916A (ja) 1982-06-23 1982-06-23 ３値レベルクロツク発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57107815A JPS58223916A (ja) 1982-06-23 1982-06-23 ３値レベルクロツク発生回路

Publications (2)

Publication Number Publication Date
JPS58223916A true JPS58223916A (ja) 1983-12-26
JPH0459807B2 JPH0459807B2 (https=) 1992-09-24

Family

ID=14468730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57107815A Granted JPS58223916A (ja) 1982-06-23 1982-06-23 ３値レベルクロツク発生回路

Country Status (1)

Country Link
JP (1) JPS58223916A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787326B1 (ko) 2005-10-26 2007-12-21 산요덴키가부시키가이샤 3치 펄스 발생 회로

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100787326B1 (ko) 2005-10-26 2007-12-21 산요덴키가부시키가이샤 3치 펄스 발생 회로

Also Published As

Publication number Publication date
JPH0459807B2 (https=) 1992-09-24

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